Power for Xilinx Versal adaptive compute acceleration platform (ACAP) reference design
PMP22165
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
See the Important Notice and Disclaimer covering reference designs and other TI resources.
Key Document
- Power for Xilinx Versal Adaptive Compute Acceleration Platform Reference Design
(PDF 4649 KB)
14 May 2020
Description
This reference design addresses Xilinx Versal adaptive compute acceleration platform (ACAP) requirements and consists of a power management integrated circuit (PMIC) for system rails plus a multiphase controller and power stages to support higher current processor loads. On-board dynamic loads on the critical outputs allow testing to Xilinx's demanding power requirements. PMP22165 along with the TPS53681 EVM is a tested solution offering performance with components to meet processor requirements for Versal’s most common use cases one and three.
Features
- 10-rail user-programmable TPS650861 PMIC for both system-level power and full design sequence management
- Full system power solution for Versal's most common use cases one and three
- Optimized power stage combination for peak efficiency of 92% on the VCCINT rail at the nominal output voltage
- On-board dynamic loads for more critical outputs
See the Important Notice and Disclaimer covering reference designs and other TI resources.
