Equalization Optimization of a JESD204B Serial Link Reference Design


Design files


Employing equalization techniques is an effective way of compensating for channel loss in JESD204B high speed serial interfaces for data converters. This reference design features the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to prepare the 7.4 Gbps serial data for transmission. Configuration allows a user to optimize the de-emphasis setting (DEM) and output voltage swing setting (VOD) of the output driver to inversely match the characteristics of the channel. Experiments demonstrate the reception of a clean data eye over 20” of FR-4 material at the full data rate.

  • Achieve a high performance JESD204B serial link using low cost PCB materials
  • Understand the limitations of lossy channels and equalization techniques to overcome the limitations
  • Use a formula-based approach to optimizing the equalization features of the ADC16DX370
  • This reference design is tested and includes an EVM, configuration software and User's Guide
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Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDU551.PDF (1256 K)

Reference design overview and verified performance test data


Detailed schematic diagram for design layout and components


Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRBP3.ZIP (2524 K)

Detailed overview of design layout for component placement

TIDRBP4.ZIP (2545 K)

Detailed overview of design layout for component placement

TIDRBP7.ZIP (1430 K)

Files used for 3D models or 2D drawings of IC components


Files used for 3D models or 2D drawings of IC components

TIDC748.ZIP (706 K)

Design file that contains information on physical board layer of design PCB

TIDRBP5.PDF (1014 K)

PCB layer plot file used for generating PCB design layout

TIDRBP6.ZIP (1259 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

High-speed ADCs (≥10 MSPS)

ADC16DX370Dual-Channel, 16-Bit, 370-MSPS Analog-to-Digital Converter (ADC)

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
Direction-controlled voltage translators

SN74AVC4T7744-bit dual-supply bus transceiver with configurable voltage-level shifting and 3-state outputs

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

LP3878-ADJ800-mA, 16-V, adjustable low-dropout voltage regulator with enable

Data sheet: PDF | HTML

LMH6521High Performance Dual DVGA

Data sheet: PDF | HTML

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Evaluation board

ADC16DX370EVM — ADC16DX370 Evaluation Module

The ADC16DX370EVM is an evaluation module used for evaluation of the ADC16DX370.  The ADC16DX370 is a low power, 16-bit, 370-MSPS analog to digital converter (ADC) with a buffered analog input, and outputs featuring a JESD204B interface operating at up to 7.4Gb/s. The EVM has (...)

User guide: PDF
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GUI for evaluation module (EVM)

ADC16DX370EVM Configuration GUI Installer (Rev. A) — SLAC657A.ZIP (174455 K)

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Technical documentation

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Type Title Date
Design guide Equalization Optimization of the ADC16DX370 JESD204B Serial Link Design Guide Oct. 23, 2014

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