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Direction-controlled voltage translators

SN74AVC4T774

ACTIVE

4-bit dual-supply bus transceiver with configurable voltage-level shifting and 3-state outputs

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Data sheet

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SN74AXC4T774 ACTIVE 4-bit dual-supply bus transceiver with 3-state outputs and independent direction control inputs Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC4T774

ACTIVE
Data sheet Order now

Product details

Technology Family AVC Applications SPI, UART, JTAG Bits (#) 4 High input voltage (Min) (Vih) 0.78 High input voltage (Max) (Vih) 3.6 Vout (Min) (V) 1.2 Vout (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog
Technology Family AVC Applications SPI, UART, JTAG Bits (#) 4 High input voltage (Min) (Vih) 0.78 High input voltage (Max) (Vih) 3.6 Vout (Min) (V) 1.2 Vout (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog
TSSOP (PW) 16 22 mm² 4.4 x 5 UQFN (RSV) 16 5 mm² 2.6 x 1.8 VQFN (RGY) 16 14 mm² 4 x 3.5
  • Each Channel Has an Independent DIR Control Input
  • Control Inputs VIH/VIL Levels are Referenced to VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.1-V to 3.6-V Power-Supply Range
  • I/Os are 4.6-V Tolerant
  • Ioff Supports Partial Power-Down-Mode Operation
  • Typical Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (<1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds the Following Levels (Tested Per JESD 22)
    • ±8000-V Human-Body Model (A114-A)
    • 250-V Machine Model (A115-A)
    • ±1500-V Charged-Device Model (C101)
  • Each Channel Has an Independent DIR Control Input
  • Control Inputs VIH/VIL Levels are Referenced to VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.1-V to 3.6-V Power-Supply Range
  • I/Os are 4.6-V Tolerant
  • Ioff Supports Partial Power-Down-Mode Operation
  • Typical Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (<1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds the Following Levels (Tested Per JESD 22)
    • ±8000-V Human-Body Model (A114-A)
    • 250-V Machine Model (A115-A)
    • ±1500-V Charged-Device Model (C101)

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.1 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.1 to 3.6 V. The SN74AVC4T774 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. This allows for universal low-voltage bi-directional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-port outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.1 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.1 to 3.6 V. The SN74AVC4T774 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. This allows for universal low-voltage bi-directional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-port outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
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Technical documentation

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Type Title Date
* Data sheet SN74AVC4T774 4-Bit Dual-Supply Bus Transceiver With Configurable Voltage-Level Shifting and 3-State Outputs With Independent Direction Control Inputs datasheet (Rev. G) PDF | HTML 03 May 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Application note Optimizing Video Doorbell Designs with Common Logic Use Cases (Rev. A) PDF | HTML 01 Apr 2021
Application note Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B) PDF | HTML 29 Mar 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
White paper Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) 01 May 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 Apr 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
More literature LCD Module Interface Application Clip 09 May 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 Jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 Aug 1998

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Not available on TI.com
Simulation model

IBIS Model for SN74AVC4T774 IBIS Model for SN74AVC4T774

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TSSOP (PW) 16 View options
UQFN (RSV) 16 View options
VQFN (RGY) 16 View options

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