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Product details

Parameters

Function Dual-loop PLL Number of outputs 15 Number of Inputs 3 RMS jitter 0.088 Output frequency (Min) (MHz) 0.289 Output frequency (Max) (MHz) 3080 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVDS, LVPECL Supply voltage (Min) (V) 3.15 Supply voltage (Max) (V) 3.45 Features JESD204B Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

WQFN (NKD) 64 81 mm² 9 x 9 open-in-new Find other Clock jitter cleaners & synchronizers

Features

  • JEDEC JESD204B Support
  • Ultra-Low RMS Jitter
    • 88 fs RMS Jitter (12 kHz to 20 MHz)
    • 91 fs RMS Jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks from PLL2
    • Up to 7 SYSREF Clocks
    • Maximum Clock Output Frequency 3.1 GHz
    • LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
  • Up to 1 Buffered VCXO/Crystal Output from PLL1
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Up to 3 Redundant Input Clocks
      • Automatic and Manual Switch-Over Modes
      • Hitless Switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode When Input Clocks are Lost
  • PLL2
    • Normalized [1 Hz] PLL Noise Floor of
      –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32
    (even and odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25-ps Step Analog Delay
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: –40 to 85°C
  • Supports 105°C PCB Temperature (Measured at Thermal Pad)
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8 mm)

All trademarks are the property of their respective owners.

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Description

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.

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Technical documentation

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No results found. Please clear your search and try again. View all 18
Type Title Date
* Datasheet LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs datasheet (Rev. AS) Sep. 27, 2017
Application notes Multi-Clock Synchronization Dec. 30, 2019
Technical articles Solving synchronization challenges in Industrial Ethernet Jul. 19, 2019
Technical articles Step-by-step considerations for designing wide-bandwidth multichannel systems Jun. 04, 2019
User guides LMK04826/28 User’s Guide (Rev. B) Mar. 13, 2018
Technical articles Preparing for 5G applications: sync your multichannel JESD204B data acquisition systems up to 15 GHz Aug. 28, 2017
Technical articles High-speed data converter clocking for JESD204B Jul. 07, 2017
Selection guides TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017
Application notes RF Sampling ADC with 800MHz of IBW LTE Sep. 08, 2016
User guides TSW12J54EVM User's Guide Oct. 21, 2015
User guides TSW54J60 Evaluation Module User's Guide (Rev. A) Sep. 21, 2015
Application notes Analog Applications Journal 2Q 2015 Apr. 28, 2015
Application notes JESD204B multi-device synchronization: Breaking down the requirements Apr. 28, 2015
Selection guides Analog for Xilinx (R) FPGAs Selection Guide - 2015 (Rev. B) Jan. 07, 2015
Application notes When is the JESD204B interface the right choice? Jan. 22, 2014
User guides HSDC-SEK-10 Jan. 17, 2013
Application notes LMK04828 as a Clock Source for the ADS42JB69 Nov. 14, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
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Description

The ADC08DJ3200 evaluation module (EVM) allows for the evaluation of the ADC08DJ3200 device. ADC08DJ3200 is a low-power, 8-bit, dual-channel 3.2-GSPS or single-channel 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with (...)

Features
  • Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
  • Easy-to-use software GUI to configure ADC08DJ3200, LMX2582, and LMK04828 devices for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High-Speed Data Converter Pro (...)
EVALUATION BOARDS Download
document-generic User guide
$1,999.00
Description

The ADC09QJ1300 evaluation module (EVM) allows for the evaluation of the ADC09QJ1300-Q1 device. ADC09QJ1300-Q1 is a low-power, 9-bit, quad-channel, 1.3-GSPS analog-to-digital converter (ADC) with a buffered analog input and integrated digital down converter with on-chip PLL, which features a (...)

Features
  • Flexible transformer-coupled analog input allows for a variety of sources and frequencies
  • Easy-to-use software GUI to configure ADC09QJ1300-Q1 and LMK04828 devices for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through high-speed data converter pro software (...)
EVALUATION BOARDS Download
document-generic User guide
Description

The ADC12DJ2700 evaluation module (EVM) allows for the evaluation of the ADC12DJ2700 device. ADC12DJ2700 is a low-power, 12-bit, dual-channel 2.7-GSPS or single-channel 5.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with (...)

Features
  • Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
  • Easy-to-use software GUI to configure ADC12DJ2700, LMX2582, and LMK04828 devices for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High-Speed Data Converter Pro (...)
EVALUATION BOARDS Download
document-generic User guide
Description

The ADC12DJ3200 evaluation module (EVM) allows for the evaluation of device ADC12DJ3200. The ADC12DJ3200 is a low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO and (...)

Features
  • Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
  • Easy-to-use software GUI to configure ADC12DJ3200, LMX2582, and LMK04828 devices for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High-Speed Data Converter Pro (...)
EVALUATION BOARDS Download
document-generic User guide
Description

The ADC12DJ5200RF evaluation module (EVM) allows for the evaluation of device ADC12DJ5200RF. The ADC12DJ5200RF is a low-power, 12-bit, dual 5.2-GSPS/single 10.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO (...)

Features
  • Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
  • Easy-to-use software GUI to configure ADC12DJ5200RF, LMX2582, and LMK04828 devices for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through high-speed data converter pro (...)
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document-generic User guide
Description

The ADC12DL3200 evaluation module (EVM) is used to evaluate the ADC12DL3200, which is a 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with an LVDS interface. The EVM has single-ended AC-coupled analog inputs, onboard ADC clock generation, and (...)

Features
  • Clocking provided by onboard LMX2582 clock synthesizer
  • 400-pin Samtec® SEARAY™ header connects directly to TSW14DL3200EVM data capture solution via LVDS interface
  • DATACONVERTERPRO-SW analysis tool provides complete environment for signal analysis, including data capture and storage of ADC EVM output
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document-generic User guide
$1,999.00
Description

The ADC12QJ1600 evaluation module (EVM) allows for the evaluation of the ADC12QJ1600-Q1 device. ADC09QJ1300-Q1 is a low-power, 12-bit, quad-channel, 1.6-GSPS analog-to-digital converter (ADC) with a buffered analog input and integrated digital down converter with on-chip PLL, which features a (...)

Features
  • Flexible transformer-coupled analog input allows for a variety of sources and frequencies
  • Easy-to-use software GUI to configure ADC12QJ1600-Q1 and LMK04828 devices for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through high-speed data converter pro software (...)
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document-generic User guide
Description

The ADC14X250EVM is an evaluation board used to evaluate the ADC14X250 analog-to-digital converter (ADC) from Texas Instruments. The ADC14X250 is a single channel 14-bit ADC capable of operating at sampling rates up to 250 Mega Samples Per Second (MSPS) with outputs featuring a standard JESD204B (...)

Features

 

  • Transformer coupled signal input network allowing a single-ended signal source
  • LMK04828 system clock generator that generates the FPGA reference clock for the high speed serial interface
  • Default transformer coupled clock input network to test the ADC performance with a very low-noise clock
  • High speed (...)
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document-generic User guide
Description

The ADC31JB68EVM is an evaluation board used to evaluate the ADC31JB68 analog-to-digital converter (ADC) from Texas Instruments. The ADC31JB68 is a single-channel 16-bit ADC capable of operating at sampling rates up to 500 Mega Samples Per Second (MSPS) with outputs featuring a standard JESD204B (...)

Features

  • Transformer-coupled signal input network allowing a single-ended signal source
  • LMK4828 system clock generator that generates the FPGA reference clock for the high speed serial interface
  • Default Transformer-coupled clock input network to test the ADC performance with a very low-noise clock
  • High speed (...)

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document-generic User guide
Description

The ADC32RF42 evaluation module (EVM) demonstrates the performance of a dual 1.5-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF42 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)

Features
  • External clocking supported, or onboard clock generation with LMK04828 generating SYSREF
  • JESD204B data interface to simplify digital interface; compliant up to 12.5-Gbps lane rates
  • Onboard power management with TI
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document-generic User guide
Description

The ADC32RF44 evaluation module (EVM) demonstrates the performance of a dual 2.5-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF44 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)

Features
  • External clocking supported, or onboard clock generation with LMK04828 generating SYSREF
  • JESD204B data interface to simplify digital interface; compliant up to 12.5-Gbps lane rates
  • Onboard power management with TI
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document-generic User guide
Description

The ADC32RF45 evaluation module (EVM) demonstrates the performance of a dual 3-GSPS 14-bit analog-to-digital conver (ADC) with the JESD204B interface. The EVM includes the ADC32RF45 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages (...)

Features

 

  • Onboard clock generation, or external clocking supported with LMK04828 generating SYSREF
  • JESD204B data interface to simplify digital interface; compliant up to 12.3-Gbps lane rates
  • Onboard power management with TI

 

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document-generic User guide
Description

The ADC32RF82 evaluation module (EVM) demonstrates the performance of a dual, 2.45-GSPS, 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF82 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the (...)

Features
  • External clocking supported or onboard clock generation with LMK04828-generating SYSREF
  • JESD204B data interface simplifies digital interface; compliant up to 12.5-GBPS lane rates
  • Onboard power management with Texas Instruments
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document-generic User guide
Description
The ADS54J20EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J20 and LMK04828 clock jitter cleaner. The ADS54J20 is a low power, 12-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface (...)
Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J20 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
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document-generic User guide
Description

The ADS54J40EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J40 and LMK04828 clock jitter cleaner. The ADS54J40 is a low power, 14-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface (...)

Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J40 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
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document-generic User guide
Description
The ADS54J42EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J42 and LMK04828 clock jitter cleaner. The ADS54J42 is a low power, 14-bit, 625-GMSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)
Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J42 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
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document-generic User guide
Description

The ADS54J64 evaluation module (EVM) is used to evaluate the ADS54J64 quad-channel, 14-bit, 1-GSPS, 2x-oversampling analog-to-digital converter (ADC). The EVM has transformer-coupled analog inputs to accommodate a wide range of signal sources and frequencies. The EVM is designed to connect (...)

Features
  • Transformer-coupled input network provides single-ended to differential signal conversion
  • LMK04828 (ultra-low jitter and phase noise clock) generates a complete JESD204B subclass 1 clocking solution simplifying the FPGA interface
  • Device registers programmed through a USB connector and FTDI USB-to-SPI (...)
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document-generic User guide
Description

The ADS54J66EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J66 and LMK04828 clock jitter cleaner. The ADS54J66 is a low power, 14-bit, 500-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J66 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
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document-generic User guide
Description

The ADS54J69EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J69 and LMK04828 clock jitter cleaner. The ADS54J69 is a low power, 16-bit, 500-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

Features
  • Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J69 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
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document-generic User guide
Description

The ADS58J64EVM is an evaluation board used to evaluate the ADS58J64 Integrated Receiver from Texas Instruments. The ADS58J64 is a low power, 14-bit, 500-MSPS, quad channel telecom receiver with a buffered analog input. The device supports JESD204B interface and data rates up to 10Gbps. The EVM has (...)

Features
  • Transformer-coupled signal input network, allows a single-ended signal source to the EVM
  • On board system clock generator (LMK04828) generates the FPGA reference clock, ADC sampling clock and SYSREFs for the high-speed JESD204B serial interface
  • Default transformer-coupled clock input network enables (...)
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document-generic User guide
Description

The AFE7422 evaluation module (EVM) is an RF-sampling transceiver platform that can be configured to support up to two-transmit and two-receive (2T2R) channels simultaneously. The module evaluates the AFE7422 device, which is a dual-channel RF-sampling analog front end (...)

Features
  • Allows evaluation of 4T4R RF-sampling AFE7422 solutions
  • JESD204B data interface to simplify digital interface; compliant up to 15-Gbps lane rates
  • Supports JESD204B subclass 1 for synchronization and compatibility
  • Option for DC-DC-based LDO-less power-management solution
  • Onboard clocking solution (...)
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document-generic User guide
Description

The AFE7444 evaluation module (EVM) is an RF-sampling transceiver platform that can be configured to support up to four-transmit and four-receive (4T4R) channels simultaneously. The module evaluates the AFE7444 device, which is a quad-channel RF-sampling analog front end (...)

Features
  • Allows evaluation of 4T4R RF-sampling AFE7444 solutions
  • JESD204B data interface to simplify digital interface; compliant up to 15-Gbps lane rates
  • Supports JESD204B subclass 1 for synchronization and compatibility
  • Option for DC-DC-based LDO-less power-management solution
  • Onboard clocking solution (...)
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$1,999.00
Description

The AFE7769-3P5 evaluation module (EVM) is a board used to evaluate the AFE77xx family of integrated RF transceivers. AFE7769 and AFE7799 devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrate phase-locked loops (PLLs) and voltage-controlled (...)

Features
  • Evaluates AFE77xx integrated transceiver family of devices
  • Simplified digital interface with JESD204B/C; supports up to 29.5-Gbps lane rates
  • JESD subclass 1 for multiple-device synchronization
  • Onboard clocking solution with optional external feed
  • Onboard power-management scheme
EVALUATION BOARDS Download
$1,999.00
Description

The AFE7769 evaluation module (EVM) is a board used to evaluate the AFE77xx family of integrated RF transceivers. AFE77xx devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrate phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs) for (...)

Features
  • Evaluates AFE77xx integrated transceiver family of devices
  • Simplified digital interface with JESD204B/C; supports up to 29.5-Gbps lane rates
  • JESD subclass 1 for multiple-device synchronization
  • Onboard clocking solution with optional external feed
  • Onboard power-management scheme
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document-generic User guide
$1,999.00
Description

The AFE7920 evaluation module (EVM) is an RF-sampling transceiver platform that can be configured to support up to four-transmit, four-receive plus two-feedback (4T4R + 2FB) channels simultaneously.

The board evaluates the AFE7920 device, which is a quad-channel RF-sampling analog front end (AFE (...)

Features
  • Allows evaluation of 4T4R + 2FB RF-sampling AFE7920 solutions
  • JESD204B/C data interface to simplify digital interface; compliant up to 29.5-Gbps lane rates
  • Supports JESD204B/C for synchronization and compatibility
  • Option for DC-DC-based LDO-less power-management solution
  • Onboard clocking solution (...)
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document-generic User guide
Description

The DAC38RF80EVM is the circuit board for evaluating DAC38RF80/84/90 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate. It is designed to work with the FPGA-based pattern generator card TSW14J56EVM (Rev B and up). The available (...)

Features
  • Allows evaluation of DAC38RF80/84/90 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with 2:1 impedance transformer for (...)
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document-generic User guide
Description
The DAC38RF82EVM is the circuit board for evaluating DAC38RF82/83/85/93 digital to analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9GSPS sampling rate and it is designed to work with the TSW14J56 EVM. The available FMC connector also makes it possible to (...)
Features
  • Allows evaluation of DAC38RF82/83/85/93 up to 9GSPS sampling rate
  • Supports up to 12.5Gbps serdes signaling rate across FMC
  • Integrated low phase noise On–chip PLL with 2 VCOs to simplify system clock generation. Also supports external clock mode.
  • AC coupled, differential output with on-board 2:1 (...)
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document-generic User guide
Description
The DAC38RF86 evaluation module (EVM) is the circuit board for evaluating DAC38RF86 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC connector also (...)
Features
  • Allows evaluation of DAC38RF86 or DAC38RF96 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (...)
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document-generic User guide
Description
The DAC38RF87 evaluation module (EVM) is the circuit board for evaluating the DAC38RF87 digital-to-analog converter (DAC). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC connector (...)
Features
  • Allows evaluation of DAC38RF87/97 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (DAC38RF87) for (...)
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document-generic User guide
Description

The DAC38RF89 evaluation module (EVM) is the circuit board for evaluating DAC38RF89 digital-to-analog converters (DACs). The DAC38RFEVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC (...)

Features
  • Allows evaluation of DAC38RF89 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (DAC38RF89) for (...)
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Description

The DEV-ADC34J22 is a four-channel, 50MSPS ADC Module designed to integrate with Altera’s HSMC standard. The DEV-ADC34J22 features TI’s new JESD204B compliant ADC34J22 Analog Digital Converter (ADC), with clocking conditioning using TI’s LMK04828 jitter cleaner. It provides (...)

Features

Board Features

  • Texas Instruments ADC34J22 Analog to Digital Converter
  • 4 channel, 12bit, 50 MSPS, JESD204B compliant ADC module
  • Two RF AC coupled input channels
  • Two Analog DC coupled input channels
  • External clock input
  • External trigger input
  • On board TI LMK04828B Dual Loop
  • Clock Jitter Cleaner Reference (...)
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document-generic User guide
$499.00
Description

The LMK04828BEVM and LMK04826BEVM evaluation modules (EVMs) support the LMK0482x family of devices. The the LMK0482x devices are the industry's highest performance clock conditioners with JEDEC JESD204B support. The dual-loop architecture of the PLLATINUM™ integrated (...)

Features
  • JEDEC JESD204B support
  • Ultra-low rms jitter performance
  • Dual-loop architecture
  • 3 redundant input clocks with LOS
  • Precision digital delay, fixed or dynamically adjustable
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document-generic User guide
$1,999.00
Description

RF Sampling 4GSPS ADC with 8GHz DC-Coupled Fully differential Amplifier. Provides a wide bandwidth high performance AC- or DC-coupled capture platform with up to 2 GHz of continous capture bandwidth. Built-in DDC functions enable tuning, down-conversion and bandwidth reduction of captured signals (...)

Features

  • 12-bit 4GSPS ADC - ADC12J4000
  • 8GHz Fully Differential Amplifier - LMH5401
  • 4.8 GHz Low Phase Noise PLL/VCO TRF3765
  • Clock Jitter Cleaner LMK04828
  • Complete TI Power Solution
  • 2GHz Butterworth Low Pass Filter Design

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document-generic User guide
Description

The TSW16DX370EVM is a reference design board used to evaluate the high performance receiver IF super-heterodyne subsystem solution including the following products from Texas Instruments:

  • TRF37B32 dual down-converting mixer with integrated IF amplifier
  • LMH6521 dual digitally controlled variable gain (...)
Features
  • High linearity, low noise Superheterodyne sub-system reference design
  • Wide RF input range and greater than 100MHz of IF bandwidth
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple connection to TSW14J56EVM data capture card or direct connection to FMC based Xilinx (...)
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document-generic User guide
$699.00
Description

The TSW38J84EVM Evaluation Module is an evaluation board that allows system designers to evaluate the performance of Texas Instruments' dual transmit signal chain consisting of the DAC38J84, TRF3722, TRF3705, and the LMK04828. For ease of use as a complete dual RF transmit solution the TSW38J84EVM (...)

Features
  • Complete bits-to-RF dual transmit signal chain solution utilizing the JESD204B interface
  • TRF3722 integrated modulator and RF synthesizer reduces solution size and simplifies layout
  • Enables evaluation of RF performance of both TRF3722 and TRF3705 modulators
  • Includes LMK04828 for onboard clock generation (...)
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document-generic User guide
$2,499.00
Description

The TSW40RF80 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF80 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The DAC38RF80 (...)

Features
  • RF-sampling transceiver utilizing the JESD204B interface
  • DAC38RF80 dual RF DAC with single-ended output
  • ADC32RF45 dual RF ADC with bypass option
  • LDO-less power-management solution
  • Onboard clocking solution; four different ADC clocking options, including TX PLL clock output
  • Interfaces with TSW14J56 or (...)
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document-generic User guide
$2,499.00
Description

The TSW40RF82 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF82 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The DAC38RF82 (...)

Features
  • RF-sampling transceiver utilizing the JESD204B interface
  • DAC38RF82 dual RF DAC with differential output
  • ADC32RF45 dual RF ADC with bypass option
  • LDO-less power-management solution
  • Onboard clocking solution; four different ADC clocking options, including TX PLL clock output
  • Interfaces with TSW14J56 or FPGA (...)
EVALUATION BOARDS Download
document-generic User guide
$899.00
Description

The TSW54J60EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J60, LMH3401, LMH6401 and LMK04828 devices. The ADS54J60 is a low power, 16-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

Features
  • Flexible transformer coupled analog input on the LMH6401 path to allow for a variety of sources and frequencies
  • Options for AC or DC coupling, single-ended or differential inputs
  • Easy to use software GUI to configure the ADS54J60, LMH6401 and LMK04828 for a variety of configurations through a USB (...)

Software development

APPLICATION SOFTWARE & FRAMEWORKS Download
Clock Design Tool - Loop Filter & Device Configuration + Simulation
CLOCKDESIGNTOOL The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
APPLICATION SOFTWARE & FRAMEWORKS Download
Texas Instruments PLLatinum Simulator Tool
PLLATINUMSIM-SW The PLLATINUMSIM-SW simulator tool lets you create detailed designs and simulations of our PLLATINUM™ integrated circuits which include the LMX series of PLLs and synthesizers.
Features
  • Part selection based on current, cost, phase noise and package
  • Filter design up for passive and active filters up to 4th-order
  • Simulation of phase noise including PLL, fractional engine, voltage-controlled oscillator (VCO), input, dividers, and loop filter
  • Simulation of spurs including phase detector (...)
APPLICATION SOFTWARE & FRAMEWORKS Download
Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Features
  • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
  • Export programming configurations for use in end application.

Design tools & simulation

SIMULATION MODELS Download
SNAM148F.ZIP (175 KB) - IBIS Model

Reference designs

REFERENCE DESIGNS Download
Scalable 20.8 GSPS reference design for 12 bit digitizers
TIDA-010128 — This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
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REFERENCE DESIGNS Download
Clocking Reference Design for RF Sampling ADCs in Signal Analyzers and Wireless Testers
TIDA-01016 — TIDA-01016 is a clocking solution for high dynamic range high speed ADC. RF input signals are directly captured using the RF sampling approach by high speed ADC. The ADC32RF45 is a dual- channel, 14-bit, 3-GSPS RF sampling ADC. The 3-dB input bandwidth is 3.2 GHz, and it captures signals up to 4 GHz (...)
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REFERENCE DESIGNS Download
1-GHz Signal Bandwidth RF Sampling Receiver Reference Design
TIDA-01161 — The RF sampling architecture offers an alternative to the traditional super-heterodyne architecture. An RF sampling analog-to-digital converter (ADC) operates at a high sampling rate and converts signals directly from radio frequencies (RF) to digital. Because of the high sampling rate, the RF (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multi-band RF Sampling Receiver Reference Design
TIDA-01163 — The RF sampling receiver captures signals directly in the radio frequency (RF) band. In a multi-band application the desired signals are not very wide band but they are spaced far apart within the spectrum. The reference design captures signals in different RF bands and digitally down-converts them (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems
TIDA-010122 — This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array RADAR and communication payload. The typical RF front end contains antenna, low noise amplifier (LNA (...)
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REFERENCE DESIGNS Download
Multichannel RF transceiver reference design for radar and electronic warfare applications
TIDA-010132 — This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that is (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
TIDA-01028 — This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
160-MHz Bandwidth Wireless Signal Tester Reference Design
TIDA-00988 — This reference design implements an IF subsystem for a standard wireless signal tester with an active balun-amplifier (LMH5401), LC bandpass filter, 16-bit ADC (ADC31JB68) and clock cleaner and generator PLL (LMK04828). Measurements using modulated signals demonstrate reception of the signal with (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers
TIDA-010131 — Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Power Supply Reference Design for Optimizing Spur and Phase Noise in RF-sampling DACs
TIDA-01215 — This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x while (...)
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REFERENCE DESIGNS Download
RF-Sampling S-Band Radar Transmitter Reference Design
TIDA-01240 — Synthesis of waveforms appropriate for an S-band multifunction phased array radar (MPAR) is demonstrated with an RF sampling architecture utilizing the DAC38RF80, a 9GSPS 16-bit digital-to-analog converter (DAC). The RF sampling transmit architecture simplifies the signal chain, bringing the data (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Direct RF-Sampling Radar Receiver for L-, S-, C-, and X-Band Using ADC12DJ3200 Reference Design
TIDA-01442 The TIDA-01442 reference design utilizes the ADC12DJ3200 evaluation module (EVM) to demonstrate a direct RF-sampling receiver for a radar operating in HF, VHF, UHF, L-, S-, C-, and part of X-band. The wide analog input bandwidth and high sampling rate (6.4 GSPS) of the analog-to-digital (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High-Bandwidth Zero-IF Reference Design for Microwave Backhaul
TIDA-01435 — The TSW40RF82EVM reference design provides a platform to interface the DAC38RF82 with a high-performance modulator - the TRF370417EVM. The TRF370417EVM can modulate wideband signals at up to 6 GHz as would be typical for a microwave backhaul application. The TRF370417 device may be substituted for a (...)
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Design files
REFERENCE DESIGNS Download
High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
TIDA-01023 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
TIDA-01021 — High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
TIDA-01024 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
TIDA-01022 — This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Efficient, LDO-Less, Power-Supply Network Reference Design for RF-Sampling ADC
TIDA-01247 TI Design TIDA-01247 demonstrates a simplified and efficient network to power an ADC32RFxx. All three power domains of the analog-to-digital converter (ADC) are supplied using a switching regulator to enable the use of a power-supply network without a low-dropout (LDO) linear regulator (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Wideband Receiver Reference Design for Upstream DOCSIS 3.1 Applications
TIDA-01378 — This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
1-GHz Bandwidth Dual Channel Transmitter up to 4-GHz Reference Design
TIDA-00409 The TSW38J84 EVM reference design provides a platform to demonstrate a wideband dual transmit solution that incorporates an integrated LO.  The reference design utilizes the 2.5 GSPS DAC38J84 device with the high performance modulators: TRF3722 (including integrated PLL/VCO) and TRF3705. The (...)
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REFERENCE DESIGNS Download
Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design
TIDA-00467 A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
RF-Sampling S-Band Radar Receiver Reference Design
TIDA-00814 — A direct RF sampling receiver approach to a radar system operating in S-band is demonstrated using the ADC32RF45, 3-Gsps, 14-bit analog to digital converter (ADC). RF sampling reduces the complexity of a system by removing down conversion and using a high sampling rate enables wider signal (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Fixed Gain Amplifier
TIDA-00823 — This reference design discusses the use and performance of the Ultra-Wideband, Fixed-gain high-speed amplifier, the LMH3401 to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Optimized Radar System Reference Design Using a DSP+ARM SoC
TIDEP0060 — For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters, who need faster time to market with increased performance and significant reduction in cost, power, and size, this reference design includes the first widely available processor integrating a (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Continuous Wave Phase-aligned Multitone Generator: DC-to-6-GHz RF-Sampling DAC Reference Design
TIDA-01084 The TIDA-01084 reference design demonstrates the use of RF sampling DAC to generate continuous phase-aligned multitone waveforms. With four 48-bit independent NCOs, the 14-bit, 9GSPS DAC38RF83 can generate four CW tones placed anywhere within the first Nyquist zone or up to 6 GHz in the second.

This (...)

document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier
TIDA-00431 Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Speed Multi-Channel ADC Clock Reference Design for Oscilloscopes, Wireless Testers and Radars
TIDA-01017 — The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
4 GHz Clock Reference Design for 12 Bit High Speed ADCs in Digital Oscilloscopes & Wireless Testers
TIDA-01015 — The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit, 4-GSPS RF sampling ADC with 3-dB input bandwidth (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High-Bandwidth Arbitrary Waveform Generator Reference Design: DC or AC coupled, High-Voltage output
TIDA-00684 — In TIDA-00684 reference design a quad-channel TSW3080 evaluation module (EVM) is developed to shows how to use an active amplifier interface with the DAC38J84 to demonstrate an arbitrary-waveform-generator frontend. The DAC38J84 provides four DAC channels with 16 bits of resolution with a maximum (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Wideband Receiver Design Using 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design
TIDEP0081 — For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
66AK2L06 DSP+ARM Processor with JESD204B Attach to Wideband ADCs and DACs
TIDEP0034 For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
50-Ohm 2-GHz Oscilloscope Front-end Reference Design
TIDA-00826 This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Variable Gain Amplifier
TIDA-00822 This reference design discusses the use and performance of the Digital Variable-Gain high-speed amplifier, the LMH6401, to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
700–2700 MHz Dual-Channel Receiver with 16-Bit ADC and 100 MHz IF Bandwidth Reference Design
TIDA-00360 The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough receiver (...)
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REFERENCE DESIGNS Download
Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
TIDA-00432 This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Clocking Solution Reference Design for GSPS ADCs
TIDA-00359 Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Equalization Optimization of a JESD204B Serial Link Reference Design
TIDA-00353 Employing equalization techniques is an effective way of compensating for channel loss in JESD204B high speed serial interfaces for data converters. This reference design features the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
JESD204B Link Latency Design Using a High Speed ADC
TIDA-00153 JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface (...)
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