EMI/EMC Compliant 10/100 Mbps Ethernet Brick with Fiber or Twisted Pair Interface Reference Design


Design files


This ethernet brick reference design provides a simplified solution that eliminates the need to have multiple boards for copper or fiber interface. It uses a small form factor, low power 10/100 Mbps ethernet transceiver to reduce board size for a cost optimized and scalable solution with reduced power consumption in high temperature industrial applications. The DP83822 provides all physical layer functions needed to transmit and receive data over both standard twisted-pair cables or connect to an external fiber optic (SC or ST or SFP) transceiver. The design provides option to configure different power supply levels for Analog and IO supply using fixed or programmable LDOs. The brick is interfaced to TM4C129X TIVA™ MCU with internal MAC. The design is tested for radiated emission, ESD and EFT as per IEC61000-4 standard level 4.

  • DP83822 ethernet PHY with fiber (100BASE-FX ) or twisted-pair (copper - 100BASETX and 10BASE-Te) interface  
  • Provision to configure analog and IO supply voltage levels separately based on application
  • Programmable LED support for link and activity
  • Meets EN55011 Class-A radiated emission requirements, and meets IEC61000-4-2 level 4 criterion B
  • D83822 works for temperature of 40oC to 125oC
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.


Reference design overview and verified performance test data

TIDRO11B.ZIP (868 K)

Detailed schematic diagram for design layout and components

TIDRO12B.ZIP (100 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRO13A.ZIP (903 K)

Detailed overview of design layout for component placement

TIDRO15B.ZIP (5458 K)

Files used for 3D models or 2D drawings of IC components


Design file that contains information on physical board layer of design PCB

TIDRO14A.ZIP (1760 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

Ethernet PHYs

DP83822HExtended temperature, robust low-power 10/100-Mbps Ethernet PHY transceiver with 16-kV ESD

Data sheet: PDF | HTML
Ethernet PHYs

DP83822HFExtended temperature, robust 10/100-Mbps Ethernet PHY transceiver with fiber support & 16-kV ESD

Data sheet: PDF | HTML
Ethernet PHYs

DP83822ILow-power, robust 10/100-Mbps Ethernet PHY transceiver with 16-kV ESD

Data sheet: PDF | HTML
Ethernet PHYs

DP83822IFLow-power, robust 10/100-Mbps Ethernet PHY transceiver with fiber support & 16-kV ESD

Data sheet: PDF | HTML
Clock buffers

CDCLVC1102Low jitter, 1:2 LVCMOS fan-out clock buffer

Data sheet: PDF | HTML
Clock generators

CDCE913Programmable 1-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs

Data sheet: PDF | HTML
ESD protection diodes

TPD4E05U06-Q1Automotive Quad 0.5-pF, 5.5-V, ±12-kV ESD protection diode for USB & High Speed Interfaces

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TL1963A-Q1Automotive 1.5-A, 20-V, adjustable low-dropout voltage regulator with reverse current protection

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS71550mA 24V ultra-low-IQ low-dropout (LDO) voltage regulator

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7542-A, ultra-low-dropout voltage regulator with power good & enable

Data sheet: PDF

Technical documentation

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Type Title Date
* Design guide EMI-Compliant, 125°C 10/100-Mbps Ethernet Brick Reference Design (Rev. C) Jan. 31, 2018
Technical article Overcoming Ethernet connectivity challenges on the power grid PDF | HTML Jun. 27, 2019
Technical article Two ways to save power with low-power Ethernet PDF | HTML Nov. 17, 2016

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