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CDCLVC1102

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Low Jitter, 1:2 LVCMOS Fan-out Clock Buffer

Data sheet
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Low Jitter, 1:2 LVCMOS Fan-out Clock Buffer

CDCLVC1102

ACTIVE
Data sheet Order now

Product details

Parameters

Function Single-ended Additive RMS jitter (Typ) (fs) 70 Output frequency (Max) (MHz) 250 Number of outputs 2 VCC out (V) 2.5, 3.3 VCC core (V) 2.5, 3.3 Output skew (ps) 50 Features 1:2 fanout, Output enable control Operating temperature range (C) -40 to 85 Rating Catalog Output type LVCMOS Input type LVCMOS open-in-new Find other Clock buffers

Package | Pins | Size

TSSOP (PW) 8 19 mm² 3 x 6.4 open-in-new Find other Clock buffers

Features

  • High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10, 1:12 LVCMOS Clock Buffer Family
  • Very Low Pin-to-Pin Skew < 50 ps
  • Very Low Additive Jitter < 100 fs
  • Supply Voltage: 3.3 V or 2.5 V
  • fmax = 250 MHz for 3.3 V
    fmax = 180 MHz for 2.5 V
  • Operating Temperature Range: –40°C to 85°C
  • Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP Package (All Pin-Compatible)

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Description

The CDCLVC11xx is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments.

The entire family is designed with a modular approach in mind. It is intended to round up TI’s series of LVCMOS clock generators.

Seven different fan-out variations, 1:2 to 1:12, are available. All of the devices are pin-compatible to each other for easy handling.

All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.

The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low.

The CDCLVC11xx family operates in a 2.5-V and
3.3-V environment and are characterized for operation from –40°C to 85°C.

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Same functionality and pinout but is not an equivalent to the compared device:
NEW LMK1C1102 ACTIVE 2-channel output LVCMOS 1.8-V buffer LMK1C1102 is parametrically superior to the CDCLVC1102, more cost-effective than the CDCLVC1102, and has added features, such as synchronous output enable.

Technical documentation

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Type Title Date
* Datasheet CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family datasheet (Rev. B) Feb. 24, 2017
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017
Application notes How to Apply 1.8-V Signals to 3.3-V CDCLVC11xx Fanout Clock Buffer Nov. 30, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
$149.00
Description
The CDCLVC1104 is a high-performance, low-additive phase noise LVCMOS clock buffer. It has one LVCMOS input and four LVCMOS outputs. It also has an enable pin. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVC1104. However, this EVM can also be used for (...)
Features
  • Easy-to-use evaluation board to fan out low-phase noise LVCMOS clock signals
  • Easy device setup
  • Enable pin configurable through jumper and SMA
  • Board powered at 2.5 V or 3.3 V
View details
EVALUATION BOARDS Download
document-generic User guide
Description
DLP® LightCrafter Display 4710 EVM-G2 is an easy to use, plug and play evaluation platform for the Full HD DLP4710 chipset. The DLP4710 chipset is designed to be used in a wide array of display applications like mobile projectors, screenless TVs, interactive displays and digital signage. The DLP4710 (...)
Features
  • 1080p HD display using DLP4710
  • Digital controller for the DLP4710 DMD, DLPC3439
  • PMIC/LED driver for the DLP4710 DMD and DLPC3439 controller, DLPA3005
  • Production ready RGB LED optical engine from YoungOptics
  • DLP4710, DLPC3439 Configuration and Support Firmware
View details

Design tools & simulation

SIMULATION MODELS Download
SLLM088B.ZIP (263 KB) - IBIS Model

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EN55011 Compliant, Industrial Temperature, 10/100Mbps Ethernet PHY Brick Reference Design
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TSSOP (PW) 8 View options

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