SLASF63 june   2023 DAC539E4W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Threshold DAC
    6. 6.6  Electrical Characteristics: Comparator
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Threshold DAC
        1. 7.3.2.1 Voltage Reference and DAC Transfer Function
          1. 7.3.2.1.1 Power-Supply as Reference
          2. 7.3.2.1.2 Internal Reference
          3. 7.3.2.1.3 External Reference
      3. 7.3.3 Look-Up Table (LUT)
      4. 7.3.4 Programming Interface
      5. 7.3.5 Nonvolatile Memory (NVM)
        1. 7.3.5.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.5.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.5.1.2 NVM-CRC-FAIL-INT Bit
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 External Reset
      8. 7.3.8 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Comparator Mode
        1. 7.4.1.1 Programmable Hysteresis Comparator
      2. 7.4.2 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 7.6.3  DAC-x-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 7.6.4  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0401h]
      5. 7.6.5  DAC-x-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      6. 7.6.6  COMMON-CONFIG Register (address = 1Fh) [reset = 1249h]
      7. 7.6.7  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      8. 7.6.8  COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      9. 7.6.9  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      10. 7.6.10 CMP-STATUS Register (address = 23h) [reset = 0000h]
      11. 7.6.11 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      12. 7.6.12 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      13. 7.6.13 STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      14. 7.6.14 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      15. 7.6.15 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      16. 7.6.16 DAC-x-DATA Register (SRAM address = 21h, 22h, 23h, 24h) [reset = 8000h]
      17. 7.6.17 LUT-x-DATA Register (SRAM address = 25h through 34h) [reset = (see register description)]
      18. 7.6.18 LOOP-WAIT Register (SRAM address = 35h) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBH|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.5.2.2.1 Address Byte

The address byte, as shown in Table 7-11, is the first byte received from the controller device following the start condition. The first four bits (MSBs) of the address are factory preset to 1001b. The next three bits of the address are controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is sampled during the first byte of each data frame to determine the address. The device latches the value of the address pin, and consequently responds to that particular address according to Table 7-12.

Table 7-11 Address Byte
COMMENT MSB LSB
— AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W
General address 1 0 0 1 See Table 7-12
(target address column)		 0 or 1
Broadcast address 1 0 0 0 1 1 1 0
Table 7-12 Address Format
TARGET ADDRESS A0 PIN
000 AGND
001 VDD
010 SDA
011 SCL

The DAC539E4W supports broadcast addressing, which is used for synchronously updating or powering down multiple DAC539E4W devices. When the broadcast address is used, the DAC539E4W responds regardless of the address pin state. Broadcast is supported only in write mode.