The DAC539E4W uses a string architecture for the threshold DACs, followed by comparators. Section 7.2 shows the DAC architecture within the block diagram, which operates from a 1.8-V to 5.5-V power supply.

The threshold DAC uses one of the following three reference options: the internal voltage reference of 1.21 V, an external reference on the MODE pin, or the power supply. The threshold DACs support multiple programmable output ranges.

The comparator outputs can be inverted using register settings. The comparator outputs can be push-pull or open-drain. The analog inputs can be configured as Hi-Z or finite impedance to support different input ranges. The comparators supports programmable hysteresis using the margin-high and margin-low register fields, and latching comparator although the margin-high and margin-low register field are not stored in the NVM. The comparator outputs are accessible internally by the device.

The DAC539E4W features a programmable state machine supporting arithmetic, logic, and timing operations, as shown in Figure 7-1. This state machine is preprogrammed as a look-up table that maps the comparator outputs to the GPOs for the DAC539E4W. The state machine is configured using the register map, and the parameters can be stored in the NVM. The state machine can be operated in standalone mode without interfacing to a processor (processor-less operation).

Figure 7-1 Smart DAC Architecture