DLPS095A November   2017  – February 2023 DLP650LE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Window Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Timing Requirements

Over GUID-AE4DE2A9-E5B3-4A57-AA68-9806B1C04145.html#GUID-AE4DE2A9-E5B3-4A57-AA68-9806B1C04145 (unless otherwise noted).
PARAMETER DESCRIPTION SIGNAL MIN TYP MAX UNIT
LVDS#T4918735-27
tC Clock cycle duration for DCLK_A LVDS 3.03 ns
tC Clock cycle duration for DCLK_B LVDS 3.03 ns
tW Pulse duration for DCLK_A LVDS 1.36 1.52 ns
tW Pulse duration for DCLK_B LVDS 1.36 1.52 ns
tSU Setup time for D_A(15:0) before DCLK_A LVDS 0.35 ns
tSU Setup time for D_A(15:0) before DCLK_B LVDS 0.35 ns
tSU Setup time for SCTRL_A before DCLK_A LVDS 0.35 ns
tSU Setup time for SCTRL_B before DCLK_B LVDS 0.35 ns
tH Hold time for D_A(15:0) after DCLK_A LVDS 0.35 ns
tH Hold time for D_B(15:0) after DCLK_B LVDS 0.35 ns
tH Setup time for SCTRL_A after DCLK_A LVDS 0.35 ns
tH Setup time for SCTRL_B after DCLK_B LVDS 0.35 ns
tSKEW Channel B relative to Channel A#T4989946-36#T4989946-37 LVDS –1.51 1.51 ns
(1) See #DLPS0721994 for timing requirements for LVDS.
(2) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0).
(3) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0).
GUID-50E87C35-09D7-4F93-8F4A-638B5BFC5A17-low.gif Figure 6-2 SCP Timing Requirements

See GUID-AE4DE2A9-E5B3-4A57-AA68-9806B1C04145.html#GUID-AE4DE2A9-E5B3-4A57-AA68-9806B1C04145 for fSCPCLK, tSCP_DS, tSCP_DH, and tSCP_PD specifications.

See GUID-AE4DE2A9-E5B3-4A57-AA68-9806B1C04145.html#GUID-AE4DE2A9-E5B3-4A57-AA68-9806B1C04145 for tr and tf specifications and conditions.

GUID-6CF52A74-AEAF-40BA-A368-897BB93BDC46-low.gif
Not to scale.
Figure 6-3 Rise Time and Fall Time
GUID-9CD0F9DB-AEF2-41C4-A294-6615724830F3-low.gif Figure 6-4 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. See #DLPS0724282.

GUID-C29E0058-5806-4DFE-BC79-A391CD652CCF-low.gif Figure 6-5 LVDS Waveform Requirements

See GUID-AE4DE2A9-E5B3-4A57-AA68-9806B1C04145.html#GUID-AE4DE2A9-E5B3-4A57-AA68-9806B1C04145 for VCM, VID, and VLVDS specifications and conditions.

GUID-13150A63-DB4E-4119-B252-7A2F971A2FC7-low.gif Figure 6-6 Timing Requirements

See #GUID-6D3E98CD-B226-4183-A413-F745CBC973F6 for timing requirements and LVDS pairs per channel (bus) defining D_P(0:x) and D_N(0:x).