DLPS095A November   2017  – February 2023 DLP650LE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Window Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
MINNOMMAXUNIT
VOLTAGE SUPPLY
VCCSupply voltage for LVCMOS core logic#DLPS07297203.03.33.6V
VCCISupply voltage for LVDS interface#DLPS07297203.03.33.6V
VOFFSETMicromirror electrode and HVCMOS voltage#DLPS0729720#DLPS07230668.258.58.75V
VMBRSTMicromirror bias / reset voltage#DLPS0729720–2726.5V
|VCC – VCCI|Supply voltage delta (absolute value)#DLPS072787900.3V
LVCMOS INTERFACE
VIHInput high voltage1.72.5VCC + 0.3V
VILInput low voltage–0.30.7V
IOHHigh level output current–20mA
IOLLow level output current15mA
tPWRDNZPWRDNZ pulse width#DLPS072574610ns
SCP INTERFACE
ƒSCPCLKSCP clock frequency#DLPS07280850500kHz
tSCP_PDPropagation delay, clock to Q, from rising-edge of SCPCLK to valid SCPDO#DLPS07297610900ns
tSCP_DSSCPDI clock setup time (before SCPCLK falling-edge)#DLPS0729761800ns
tSCP_DHSCPDI hold time (after SCPCLK falling-edge)#DLPS0729761900ns
tSCP_NEG_ENZTime between falling-edge of SCPENZ and the rising-edge of SCPCLK.#DLPS0728081us
SCP_POS_ENZTime between falling-edge of SCPCLK and the rising-edge of SCPENZ1us
tSCP_OUT_ENTime required for SCP output buffer to recover after SCPENZ (from tristate)192/ƒDCLKs
tSCP_PW_ENZSCPENZ inactive pulse width (high level)11/ƒscpclk
trRise Time (20% to 80%). See #DLPS0729761.200ns
tfFall time (80% to 20%). See #DLPS0729761.200ns
LVDS INTERFACE
ƒCLOCKClock frequency for LVDS interface (all channels), DCLK#DLPS0725806320330MHz
|VID|Input differential voltage (absolute value)#DLPS072398100400600mV
VCMCommon mode voltage#DLPS0723981200mV
VLVDSLVDS voltage#DLPS07239802000mV
tLVDS_RSTZTime required for LVDS receivers to recover from PWRDNZ10ns
ZINInternal differential termination resistance95105Ω
ZLINELine differential impedance (PWB/trace)859095Ω
ENVIRONMENTAL
TARRAYArray temperature, long-term operational#DLPS0724684#DLPS0723629#DLPS07296781040 to 70#DLPS0723159°C
Array temperature, short-term operational#DLPS0723629#DLPS0725797010°C
TWINDOWWindow temperature (all part numbers except *1280-6434B)#T4918735-26#GUID-0E9B519B-D264-4A20-838A-05A44623B6AB1090°C
Window temperature (part number 1280-6434B)#T4918735-26 10 85
T|DELTA |Absolute temperature delta between any point on the window edge and the ceramic test point TP1#DLPS072491426°C
TDP -AVGAverage dew point average temperature (non-condensing)#DLPS072571628°C
TDP-ELRElevated dew point temperature range (non-condensing)#DLPS07231112836°C
CTELRCumulative time in elevated dew point temperature range24Months
ILLUVIllumination Wavelengths < 395 nm#DLPS07246840.682.00mW/cm2
ILLVISIllumination Wavelengths between 395 nm and 800 nmThermally limitedmW/cm2
ILLIRIllumination Wavelengths > 800 nm10mW/cm2
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than the specified limit. See GUID-3620274A-944B-4FD2-AA2C-4133B821C88E.html#GUID-3620274A-944B-4FD2-AA2C-4133B821C88E, GUID-52470D36-42D6-4545-A2D6-73353F154BF9.html#DLPS0729748, and Table 9-2.
(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin.
(5) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(9) Simultaneous exposure of the DMD to the maximum #GUID-AE4DE2A9-E5B3-4A57-AA68-9806B1C04145 for temperature and UV illumination will reduce device lifetime.
(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in GUID-F5D0F44B-69C2-4C43-A3B8-A4890F51FD35.html#DLPS0729630 and the package thermal resistance using GUID-F5D0F44B-69C2-4C43-A3B8-A4890F51FD35.html#GUID-F5D0F44B-69C2-4C43-A3B8-A4890F51FD35.
(11) Long-term is defined as the usable life of the device.
(12) Per #DLPS0721904, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See GUID-0592D37A-C011-4388-A4C0-91874C92D22F.html#GUID-0592D37A-C011-4388-A4C0-91874C92D22F for a definition of micromirror landed duty cycle.
(13) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.
(14) The locations of thermal test points TP2, TP3, TP4, and TP5 in GUID-F5D0F44B-69C2-4C43-A3B8-A4890F51FD35.html#DLPS0729630 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(15) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.
(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in GUID-F5D0F44B-69C2-4C43-A3B8-A4890F51FD35.html#DLPS0729630. The window test points TP2, TP3, TP4, and TP5 shown in GUID-F5D0F44B-69C2-4C43-A3B8-A4890F51FD35.html#DLPS0729630 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(17) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.
(18) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
GUID-E47D1640-BD02-4BCD-9A42-A9E55B3E6BBF-low.gifFigure 6-1 Maximum Recommended Array Temperature—Derating Curve