SNLS656D August   2020  – December 2023 DP83TD510E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Auto-Negotiation (Speed Selection)
      2. 6.3.2  Repeater Mode
      3. 6.3.3  Media Converter
      4. 6.3.4  Clock Output
      5. 6.3.5  Media Independent Interface (MII)
      6. 6.3.6  Reduced Media Independent Interface (RMII)
      7. 6.3.7  RMII Low Power 5-MHz Mode
      8. 6.3.8  RGMII Interface
      9. 6.3.9  Serial Management Interface
      10. 6.3.10 Extended Register Space Access
        1. 6.3.10.1 Read (No Post Increment) Operation
        2. 6.3.10.2 Read (Post Increment) Operation
        3. 6.3.10.3 Write (No Post Increment) Operation
        4. 6.3.10.4 Write (Post Increment) Operation
      11. 6.3.11 Loopback Modes
        1. 6.3.11.1 MII Loopback
        2. 6.3.11.2 PCS Loopback
        3. 6.3.11.3 Digital Loopback
        4. 6.3.11.4 Analog Loopback
        5. 6.3.11.5 Far-End (Reverse) Loopback
      12. 6.3.12 BIST Configurations
      13. 6.3.13 Cable Diagnostics
        1. 6.3.13.1 TDR
        2. 6.3.13.2 Fast Link Down Functionality
    4. 6.4 Device Functional Modes
      1. 6.4.1 Straps Configuration
        1. 6.4.1.1 Straps for PHY Address
    5. 6.5 Programming
    6. 6.6 MMD Register Address Map
    7. 6.7 DP83TD510E Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Termination Circuit
        1. 7.2.1.1 Termination Circuit for Intrinsic Safe Applications
        2. 7.2.1.2 Components Range for Power Coupling/Decoupling
        3. 7.2.1.3 Termination Circuit for Non-Intrinsic Safe Applications
        4. 7.2.1.4 CMC Specifications
      2. 7.2.2 Design Requirements
        1. 7.2.2.1 Clock Requirements
          1. 7.2.2.1.1 Oscillator
          2. 7.2.2.1.2 Crystal
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Signal Traces
        2. 7.4.1.2 Return Path
        3. 7.4.1.3 Metal Pour
        4. 7.4.1.4 PCB Layer Stacking
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

PINTYPEDESCRIPTION
NAMENO
DVDD1ADigital supply 1.0 V
  • For single-supply operation: Short this pin with CEXT (Pin 2)
  • Optional (dual-supply operation): Connect external 1.0 V to achieve lowest power
Refer to Power Connection Diagram in Application section
CEXT2AExternal capacitor for internal LDO
  • For single-supply operation: Connect 0.01- μF capacitor and short it with pin 1
  • For dual-supply operation, leave unconnected
Refer to Power Connection Diagram in Application section
VDDA3ASupply 3.3 V to support both 2.4-V p2p and 1-V p2p mode.

Supply 1.8 V to support only 1-V p2p mode.

Supplied voltage will be reflected in bit 13 of auto negotiation base page as capability to support 2.4-V p2p or 1-V p2p.

0x20E, bit 13 = 1 when 3.3 V is selected.

0x20E, bit 13 = 0 when 1.8 V is selected.

Ensure the Strap7 "Reach Selection" strap is selected appropriately to request the output voltage level in the auto negotiation page.

TX+4ATX+, TX- : Differential Transmit Output (PMD): These differential outputs are configured to 2.4-V p2p or 1-V p2p mode based on configuration chosen for PHY and auto negotiation with Link Partner.
RX+5ARX+, RX- : These differential inputs are automatically configured to accept 2.4-V p2p or 1-V p2p mode based on configuration chosen for PHY.
RX-6A
TX-7ATX+, TX- : Differential Transmit Output (PMD): These differential outputs are configured to 2.4-V p2p or 1-V p2p mode based on configuration chosen for PHY and auto negotiation with Link Partner.
GPIO28StrapGPIO: This pin can be configured for multiple configuration thru register configuration. It has mandatory PU or PD strap. Refer to Straps sections for details.
XO9 ACrystal Output: Reference Clock output. XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI.
XI/50MHzIn10 ACrystal / Oscillator Input Clock

MII, RMII master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock

RMII slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock

MDIO11Management Data I/O: Bi-directional management data signal that may be source by the management station or the PHY. This pin requires an external pull of 2.2kΩ - 4.0 kΩ.
MDC12Management Data Clock: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 1.75 MHz.
RX_D313StrapReceive Data: Symbols received on the cable are decoded and presented on these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is received in MII modes. 2-bits RX_D[1:0] is received in RMII mode.
RX_D214Strap
RX_D115Strap
RX_D016Strap
VDDIO17 PowerI/O Supply : 3.3 V/2.5 V/1.8 V. For decoupling capacitor requirements, refer to Power Connection Diagram in Application section.
RX_DV/CRS_DV18Strap

Receive Data Valid: This pin indicates valid data is present on the RX_D[3:0] for MII mode and on RX_D[1:0] for RMII mode. In RMII mode, this pin acts as CRS_DV and combines the RMII arrier and Receive Data Valid indications. This pin can be configured to RX_DV to enable RMII repeater mode using strap or register configuration.

RGMII mode: RGMII Receive Control: RX_CTRL combines receive data valid and receive error signals. RX_DV is presented on the rising edge of RX_CLK and RX_ER on the falling edge of RX_CLK.
RX_CLK/50MHz_RMII_M19MII Receive Clock: MII Receive Clock provides a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the received data stream.

In RMII master mode, this provides 50-MHz reference clock. In RMII slave mode, this pin is not used and remains Input/PD.

RGMII Receive Clock: RGMII Receive Clock provides a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the receive data stream.
RX_ER20StrapReceive Error: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. RX_ERR is asserted high for every reception error, including errors during Idle.

Unused in RGMII mode.

PWDN/INT21Power Down(Default)/Interrupt: The default function of this pin is power down. Register access is required to configure this pin as an interrupt. In power down function, an active low signal on this pin places the device in power down mode. When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup (9.5 kΩ). Some applications may require an external PU resistor.
TX_CLK22

MII Transmit Clock: MII Transmit Clock provides a 2.5-MHz reference clock for 10-Mbps speed.

Unused in RMII mode.

RGMII Transmit Clock: The clock is sourced from the MAC layer to the PHY. When operating at 10-Mbps speed, this clock must be 2.5-MHz.
TX_EN23

Transmit Enable: TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D[3:0] in MII mode and on TX_D[1:0] in RMII mode. TX_EN is an active high signal.

RGMII Transmit Control: TX_CTRL combines transmit enable and transmit error signals. TX_EN is presented on the rising edge of TX_CLK and TX_ER on the falling edge of TX_CLK.
TX_D024Transmit Data: In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK. In RMII Master mode,TX_D[0,1] are synchronous to CLKOUT50M output of the device

In RMII Slave mode, TX_D[0,1] are synchronous to rising edge of Ref clock

TX_D125
TX_D226
TX_D327
LED_2/TX_ER28Strap

This pin acts as LED_2 by default. It can be configured as GPIO or TX_ER as well. The LED is ON when link is negotiated for 10M (short reach). LED remains OFF otherwise.

LED_029StrapLED : Activity Indication LED indicates transmit and receive activity in addition to the status of the link. The LED is ON when link is good. The LED blinks when the transmitter or receiver is active. This pin can also act as GPIO using register configuration.
CLKOUT/LED_130This pin provides Reference CLKOUT of 25 MHz as default to clock other module on the board. The pin can be configured to act as LED_1 using strap or register configuration. The LED is ON when link is negotiated for 10M (long reach). The LED remains OFF otherwise. When configured for CLK_OUT, reference clock is not affected by reset.
RST_N31RST_N: This pin is an active low reset input. Asserting this pin low for at least 25μs will force a reset process to occur. Initiation of reset causes strap pins to be re-scanned and resets all the internal registers of the PHY to default value.
GPIO132StrapGeneral Purpose Input or Output.
Table 4-1 Internal PU/PD in various states
Pin #

Pin Name

Reset StateActive State ( MII Mode)Active State ( RMII Master Mode)Active State ( RMII Slave Mode)Active State (RGMII Mode)
1

DVDD

AAAAA
2

CEXT

AAAAA
3

VDDA

AAAAA
4

TX+

AAAAA
5

RX+

AAAAA
6

RX-

AAAAA
7

TX-

AAAAA
8

GPIO2

I,PDI,PDI,PDI,PDI,PD
9

XO

A

A

A

A

A

10

XI/50MHzIn

A

A

A

A

A

11

MDIO

IOIOIOIOIO
12

MDC

IIIII
13

RX_D3

I,PDO,Hi-ZI,PDI,PDO,Hi-Z
14

RX_D2

I,PD

O,Hi-Z

I,PDI,PD

O,Hi-Z

15

RX_D1

I,PDO,Hi-ZO,Hi-ZO,Hi-ZO,Hi-Z
16

RX_D0

I,PDO,Hi-ZO,Hi-ZO,Hi-ZO,Hi-Z
17

VDDIO

AAAAA
18

RX_DV/CRS_DV

I,PDO,Hi-ZO,Hi-ZO,Hi-ZO,Hi-Z
19

RX_CLK/50MHz)RMII_M

I,PDO,Hi-ZO,Hi-ZO,Hi-ZO,Hi-Z
20

RX_ER

I,PDO,Hi-ZO,Hi-ZO,Hi-ZI,PD
21

PWDN/INT

I,PU-9.5KΩ/OPEN DRAINI,PU-9.5KΩ/OPEN DRAINI,PU-9.5KΩ/OPEN DRAINI,PU-9.5KΩ/OPEN DRAINI,PU-9.5KΩ/OPEN DRAIN
22

TX_CLK

I,PDO,Hi-ZI,PDI,PDI,PD
23

TX_EN

I,PDI,PDI,PDI,PDI,PD
24

TX_D0

I,PDI,PDI,PDI,PDI,PD
25

TX_D1

I,PDI,PDI,PDI,PDI,PD
26

TX_D2

I,PDI,PDI,PDI,PDI,PD
27

TX_D3

I,PDI,PDI,PDI,PDI,PD
28

LED_2/TX_ER

I,PDO,Hi-ZO,Hi-ZO,Hi-ZO,Hi-Z
29

LED_0

I,PDO,Hi-ZO,Hi-ZO,Hi-ZO,Hi-Z
30

CLKOUT/LED_1

I,PD(Only at POR)O,Hi-ZO,Hi-ZO,Hi-ZO,Hi-Z
31

RST_N

I,PUI,PUI,PUI,PUI,PU
32

GPIO1

I,PDO,Hi-ZO,Hi-ZO,Hi-ZO,Hi-Z
The definitions below define the functionality of the I/O cells for each pin. (a) Type: I - Input (b) Type: O - Output (c) Type: I/O - Input/Output (d) Type OD - Open Drain (e) Type: PD, PU - Internal Pulldown/Pullup (g) Type HI-Z : floating (h) Type:A - Analog