SLVSET1 August 2018 DRV8873
PRODUCTION DATA.
IC4 control is shown in Figure 35 and described in Table 27.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | EN_OLP | OLP_DLY | EN_OLA | ITRIP_LVL | DIS_ITRIP | ||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-10b | R/W-00b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RSVD | R/W | 0b |
Reserved |
6 | EN_OLP | R/W | 0b |
Write 1b to run open load diagnostic in standby mode. When open load test is complete EN_OLP returns to 0b (status check) |
5 | OLP_DLY | R/W | 0b |
0b = Open load diagnostic delay is 300 µs 1b = Open load diagnostic delay is 1.2 ms |
4 | EN_OLA | R/W | 0b |
0b = Open load diagnostic in active mode is disabled 1b = Enable open load diagnostics in active mode |
3-2 | ITRIP_LVL | R/W | 10b |
00b = 4 A 01b = 5.4 A 10b = 6.5 A 11b = 7 A |
1-0 | DIS_ITRIP | R/W | 00b |
00b = Current regulation is enabled 01b = Current regulation is disabled for OUT1 10b = Current regulation is disabled for OUT2 11b = Current regulation is disabled for both OUT1 and OUT2 |