SLVSET1 August 2018 DRV8873
PRODUCTION DATA.
In this mode, after a TSD event all the outputs (OUTx) are disabled and the nFAULT pin is driven low. The FAULT and TSD bits are latched high in the SPI register. Normal operation resumes (motor-driver operation and the nFAULT line released) when the TSD condition is removed and a clear faults command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse. This mode is the default mode for a TSD event in the SPI version of the device.