SLVSDS7B August   2019  – November 2019 DRV8876

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Control Modes
        1. 7.3.2.1 PH/EN Control Mode (PMODE = Logic Low)
        2. 7.3.2.2 PWM Control Mode (PMODE = Logic High)
        3. 7.3.2.3 Independent Half-Bridge Control Mode (PMODE = Hi-Z)
      3. 7.3.3 Current Sense and Regulation
        1. 7.3.3.1 Current Sensing
        2. 7.3.3.2 Current Regulation
          1. 7.3.3.2.1 Fixed Off-Time Current Chopping
          2. 7.3.3.2.2 Cycle-By-Cycle Current Chopping
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 VM Supply Undervoltage Lockout (UVLO)
        2. 7.3.4.2 VCP Charge Pump Undervoltage Lockout (CPUV)
        3. 7.3.4.3 OUTx Overcurrent Protection (OCP)
        4. 7.3.4.4 Thermal Shutdown (TSD)
        5. 7.3.4.5 Fault Condition Summary
      5. 7.3.5 Pin Diagrams
        1. 7.3.5.1 Logic-Level Inputs
        2. 7.3.5.2 Tri-Level Inputs
        3. 7.3.5.3 Quad-Level Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Low-Power Sleep Mode
      3. 7.4.3 Fault Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Primary Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Current Sense and Regulation
          2. 8.2.1.2.2 Power Dissipation and Output Current Capability
          3. 8.2.1.2.3 Thermal Performance
            1. 8.2.1.2.3.1 Steady-State Thermal Performance
            2. 8.2.1.2.3.2 Transient Thermal Performance
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternative Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Current Sense and Regulation
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 HTSSOP Layout Example
      2. 10.2.2 VQFN Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2.3.1 Steady-State Thermal Performance

"Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time.Figure 21, Figure 22, Figure 23, and Figure 24 show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB for the HTSSOP package. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout.

DRV8876 4L_RthJA_HTSSOP.gifFigure 21. HTSSOP, 4-layer PCB junction-to-ambient thermal resistance vs copper area
DRV8876 2L_RthJA_HTSSOP.gifFigure 23. HTSSOP, 2-layer PCB junction-to-ambient thermal resistance vs copper area
DRV8876 4L_PsiJB_HTSSOP.gifFigure 22. HTSSOP, 4-layer PCB junction-to-board characterization parameter vs copper area
DRV8876 2L_PsiJB_HTSSOP.gifFigure 24. HTSSOP, 2-layer PCB junction-to-board characterization parameter vs copper area

Figure 25 and Figure 26 show how RθJA and ΨJB vary with the bottom layer copper area for the VQFN package mounted on a 2-layer board. In the case of the 4-layer board, the top-layer copper area cannot be varied. Figure 29 and Figure 30 at 1000 s show the steady-state RθJA of the 4-layer board.

DRV8876 2L_RthJA_QFN.gifFigure 25. VQFN, 2-layer PCB junction-to-ambient thermal resistance vs copper area
DRV8876 2L_PsiJB_QFN.gifFigure 26. VQFN, 2-layer PCB junction-to-board characterization parameter vs copper area