SNLS426F August   2012  – November 2018 DS125BR800

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Description (cont.)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics: Serial Management Bus Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
      2. 8.3.2 PCIe Signal Integrity
        1. 8.3.2.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
          1. 8.3.2.1.1 Signal Detect Control for Datarates above 8 Gbps
        2. 8.3.2.2 MODE Operation with SMBus Registers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Mode
    5. 8.5 Programming
      1. 8.5.1 SMBus Master Mode
      2. 8.5.2 Transfer of Data Via the SMBus
      3. 8.5.3 System Management Bus (SMBus) and Configuration Registers
      4. 8.5.4 SMBus Transactions
      5. 8.5.5 Writing a Register
      6. 8.5.6 Reading a Register
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics(1)(2)(3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PD Power Dissipation VDD = 2.5-V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PWDN = 0		 500 700 mW
VIN = 3.3-V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PWDN = 0		 660 900 mW
LVCMOS / LVTTL DC SPECIFICATIONS
VIH25 High Level Input Voltage 2.5 V-Mode 2 VDD V
VIH33 High Level Input Voltage 3.3 V-Mode 2 VIN V
VIL Low Level Input Voltage 0 0.8 V
VOH High Level Output Voltage
(ALL_DONE pin)		 Ioh= –4 mA 2 V
VOL Low Level Output Voltage
(ALL_DONE pin)		 Iol= 4 mA 0.4 V
IIH Input High Current (PWDN pin) VIN = 3.6 V, LVCMOS = 3.6 V –15 15 µA
Input High Current with internal resistors (4-level input pin) 20 150 µA
IIL Input Low Current (PWDN pin) VIN = 3.6 V, LVCMOS = 0 V –15 15 µA
Input Low Current with internal resistors (4-level input pin) –160 –40 µA
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLRX-DIFF RX Differential return loss 0.05 - 7.5 GHz –15 dB
7.5 - 15 GHz -5 dB
RLRX-CM RX Common mode return loss 0.05 - 5 GHz –10 dB
ZRX-DC RX DC common mode impedance Tested at VDD = 2.5 V 40 50 60 Ω
ZRX-DIFF-DC RX DC differential mode impedance Tested at VDD = 2.5 V 80 100 120 Ω
VRX-DIFF-DC Differential RX peak to peak voltage (VID) Tested at pins 1.2 V
VRX-SIGNAL-DET-DIFF-PP Signal detect assert level for active data signal SD_TH = float,
0101 pattern at 8 Gbps		 180 mVp-p
VRX-IDLE-DET-DIFF-PP Signal detect de-assert level for electrical idle SD_TH = float,
0101 pattern at 8 Gbps		 110 mVp-p
HIGH SPEED OUTPUTS
VTX-DIFF-PP Output Voltage Differential Swing Differential measurement with OUT_n+ and OUT_n-,
terminated by 50 Ω to GND,
AC-Coupled, VID = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0(5) 		0.8 1 1.2 Vp-p
VTX-DE-RATIO_3.5 TX de-emphasis ratio VOD = 1.0 Vp-p,
DEM0 = 0, DEM1 = R
PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps)		 –3.5 dB
VTX-DE-RATIO_6 TX de-emphasis ratio VOD = 1.0 Vp-p,
DEM0 = R, DEM1 = R
PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps)		 -6 dB
TTX-DJ Deterministic Jitter VID = 800 mV, PRBS15 pattern, 8.0 Gbps, VOD = 1.0 V, EQ = 0x00, DE = 0 dB, (no input or output trace loss) 0.05 UIpp
TTX-RJ Random Jitter VID = 800 mV, 0101 pattern, 8.0 Gbps, VOD = 1.0 V, EQ = 0x00, DE = 0 dB, (no input or output trace loss) 0.3 ps RMS
TTX-RISE-FALL TX rise/fall time 20% to 80% of differential output voltage 35 45 ps
TRF-MISMATCH TX rise/fall mismatch 20% to 80% of differential output voltage 0.01 0.1 UI
RLTX-DIFF TX Differential return loss 0.05 - 7.5 GHz –15 dB
7.5 - 15 GHz –5 dB
RLTX-CM TX Common mode return loss 0.05 - 5 GHz –10 dB
ZTX-DIFF-DC DC differential TX impedance 100 Ω
VTX-CM-AC-PP TX AC common mode voltage VOD = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0		 100 mVp-p
ITX-SHORT TX short circuit current limit Total current the transmitter can supply when shorted to VDD or GND 20 mA
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute delta of DC common mode voltage during L0 and electrical idle 100 mV
VTX-CM-DC-LINE-DELTA Absolute delta of DC common mode voltgae between TX+ and TX- 25 mV
TTX-IDLE-DATA Max time to transition to differential DATA signal after IDLE VID = 1.0 Vp-p, 8 Gbps 3.5 ns
TTX-DATA-IDLE Max time to transition to IDLE after differential DATA signal VID = 1.0 Vp-p, 8 Gbps 6.2 ns
TPLHD/PHLD Differential Propagation Delay EQ = 00(4) 200 ps
TLSK Lane to lane skew T = 25°C, VDD = 2.5 V 25 ps
TPPSK Part to part propagation delay skew T = 25°C, VDD = 2.5 V 40 ps
EQUALIZATION
DJE1 Residual deterministic jitter at 12 Gbps 30in 5mils FR4, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB		 0.18 UIpp
DJE2 Residual deterministic jitter at 8 Gbps 30in 5mils FR4, VID = 0.6 Vp-p,
PRBS15,EQ = 0x07, DEM = 0 dB		 0.11 UIpp
DJE3 Residual deterministic jitter at 5 Gbps 30in 5mils FR4, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB		 0.07 UIpp
DJE4 Residual deterministic jitter at 12 Gbps 5m 30 awg cable, VID = 0.6 Vp-p,
PRBS15, EQ = 0x07, DEM = 0 dB		 0.25 UIpp
DJE5 Residual deterministic jitter at 5 Gbps 8m 30 awg cable, VID = 0.6 Vp-p,
PRBS15, EQ = 0x0F, DEM = 0 dB		 0.33 UIpp
DE-EMPHASIS — PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps)
DJD1 Residual deterministic jitter at 12 Gbps Input Channel: 20in 5mils FR4,
Output Channel: 10in 5mils FR4
VID = 0.6 Vp-p,
PRBS15, EQ = 0x03,
VOD = 1.0 Vp-p, DEM = –3.5 dB		 0.1 UIpp
(1) Typical values represent most likely parametric norms at VDD = 2.5 V, TA = 25°C., and at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
(3) Specified by device characterization.
(4) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the longest propagation delays.
(5) In PCIe Gen-3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output VOD level set by DEMA/B[1:0] in this MODE is dependent on the VID level and the frequency content. The DS125BR800 repeater is designed to be non-limiting in this MODE, so the TX-FIR (de-emphasis) is passed to the RX to support the handshake negotiation link training.