SNLS426F August   2012  – November 2018 DS125BR800

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Description (cont.)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics: Serial Management Bus Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
      2. 8.3.2 PCIe Signal Integrity
        1. 8.3.2.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
          1. 8.3.2.1.1 Signal Detect Control for Datarates above 8 Gbps
        2. 8.3.2.2 MODE Operation with SMBus Registers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Mode
    5. 8.5 Programming
      1. 8.5.1 SMBus Master Mode
      2. 8.5.2 Transfer of Data Via the SMBus
      3. 8.5.3 System Management Bus (SMBus) and Configuration Registers
      4. 8.5.4 SMBus Transactions
      5. 8.5.5 Writing a Register
      6. 8.5.6 Reading a Register
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6 Register Maps

Table 10. SMBUS Slave Mode Register Map

Address Register Name Bit Field Type Default EEPROM Bit Description
0x00 Device Address Observation 7 Reserved R/W 0x00 Set bit to 0.
6:3 Address Bit
AD[3:0]		 R Observation of AD[3:0] bit
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
2 EEPROM Read Done R 1: Device completed the read from external EEPROM.
1:0 Reserved R/W Set bits to 0.
0x01 PWDN Channels 7:0 PWDN CHx R/W 0x00 Yes Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
[2]: CH2 – CHB_2
[1]: CH1 – CHB_1
[0]: CH0 – CHB_0
0x00 = all channels enabled
0xFF = all channels disabled
Note: override PWDN pin.
0x02 Override
PWDN Control		 7:1 Reserved R/W 0x00 Set bits to 0.
0 Override PWDN Yes 1: Block PWDN pin control
0: Allow PWDN pin control
0x03 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x04 Reserved 7:0 Reserved R/W 0x00 Yes Set bits to 0
0x05 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x05 Reserved 7:0 Reserved R/W 0x00 Reserved
0x06 Slave Register Control 7:5 Reserved R/W 0x10 Set bits to 0.
4 Reserved Yes Set bit to 1.
3 Register Enable 1 = Enable SMBus Register Control
0 = Disable SMBus Register Control
Note: In order to change VOD, DEM, and EQ of the channels in slave mode, this bit must be set to 1.
2:0 Reserved Set bits to 0.
0x07 Digital Reset and Control 7 Reserved R/W 0x01 Set bit to 0.
6 Reset Registers Self clearing bit, set to 1 to reset the register to default values
5 Reset SMBus Master Self clearing reset to SMBus master state machine
4:0 Reserved Set bits to 0 0001'b.
0x08 Override
Pin Control 		7 Reserved R/W 0x00 Set bit to 0.
6 Override SD_TH Yes 1: Block SD_TH pin control
0: Allow SD_TH pin control
5 Reserved Yes Set bit to 0.
4 Override IDLE Yes 1: IDLE control by registers
0: IDLE control by signal detect
3 Override RXDET Yes 1: Block RXDET pin control
0: Allow RXDET pin control
2 Override MODE Yes 1: Block MODE pin control
0: Allow MODE pin control
1 Reserved Set bit to 0.
0 Reserved Set bit to 0.
0x09 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x0A Signal Detect Monitor 7:0 SD_TH Status R 0x00 CH7 - CH0 Internal Signal Detector Indicator
[7]: CH7 - CHA_3
[6]: CH6 - CHA_2
[5]: CH5 - CHA_1
[4]: CH4 - CHA_0
[3]: CH3 - CHB_3
[2]: CH2 - CHB_2
[1]: CH1 - CHB_1
[0]: CH0 - CHB_0
0 = Signal detected at input (active data)
1 = Signal not detected at input (idle state)
NOTE: These bits only function when RATE pin = FLOAT
0x0B Reserved 7 Reserved R/W 0x00 Set bits to 0
6:0 Reserved R/W 0x70 Yes Set bits to 111 0000'b
0x0C Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x0D CH0 - CHB0
Signal Detect		 7:3 Reserved R/W 0x00 Set bits to 0.
2 SD Reset 1: Force signal detect "off"
0: Normal operation
1 SD Preset 1: Force signal detect "on"
0: Normal operation
0 Reserved Set bit to 0.
0x0E CH0 - CHB0
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0.
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2 RXDET Yes 00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0 Reserved Set bits to 0.
0x0F CH0 - CHB0
EQ		 7:0 EQ Control R/W 0x2F Yes IB0 EQ Control - total of 256 levels.
See Table 2.
0x10 CH0 - CHB0
VOD 		7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 MODE_SEL Yes 1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3 Reserved Yes Set bits to default value - 101.
2:0 VOD Control Yes OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x11 CH0 - CHB0
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH0 - CHB0.
1: RX = detected
0: RX = not detected
6:5 MODE_DET STATUS R Observation bit for MODE_DET CH0 - CHB0.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W Yes OB0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x12 CH0 - CHB0
IDLE Threshold		 7:4 Reserved R/W 0x00 Set bits to 0.
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0 IDLE thd Yes De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x13 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x14 CH1 - CHB1
Signal Detect		 7:3 Reserved R/W 0x00 Set bits to 0.
2 SD Reset 1: Force signal detect "off"
0: Normal operation
1 SD Preset 1: Force signal detect "on"
0: Normal operation
0 Reserved Set bit to 0.
0x15 CH1 - CHB1
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0.
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2 RXDET Yes 00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0 Reserved Set bits to 0.
0x16 CH1 - CHB1
EQ		 7:0 EQ Control R/W 0x2F Yes IB1 EQ Control - total of 256 levels.
See Table 2.
0x17 CH1 - CHB1
VOD 		7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 MODE_SEL Yes 1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3 Reserved Yes Set bits to default value - 101.
2:0 VOD Control Yes OB1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x18 CH1 - CHB1
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH1 - CHB1.
1: RX = detected
0: RX = not detected
6:5 MODE_DET STATUS R Observation bit forMODE_DET CH1 - CHB1.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W Yes OB1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x19 CH1 - CHB1
IDLE Threshold		 7:4 Reserved R/W 0x00 Set bits to 0.
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0 IDLE thd Yes De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x1A Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x1B CH2 - CHB2
Signal Detect		 7:3 Reserved R/W 0x00 Set bits to 0.
2 SD Reset 1: Force signal detect "off"
0: Normal operation
1 SD Preset 1: Force signal detect "on"
0: Normal operation
0 Reserved Set bit to 0.
0x1C CH2 - CHB2
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0.
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2 RXDET Yes 00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0 Reserved Set bits to 0.
0x1D CH2 - CHB2
EQ		 7:0 EQ Control R/W 0x2F Yes IB2 EQ Control - total of 256 levels.
See Table 2.
0x1E CH2 - CHB2
VOD 		7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 MODE_SEL Yes 1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3 Reserved Yes Set bits to default value - 101.
2:0 VOD Control Yes OB2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x1F CH2 - CHB2
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH2 - CHB2.
1: RX = detected
0: RX = not detected
6:5 MODE_DET STATUS R Observation bit for MODE_DET CH2 - CHB2.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W Yes OB2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x20 CH2 - CHB2
IDLE Threshold		 7:4 Reserved R/W 0x00 Set bits to 0.
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0 IDLE thd Yes De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x21 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x22 CH3 - CHB3
Signal Detect		 7:3 Reserved R/W 0x00 Set bits to 0.
2 SD Reset 1: Force signal detect "off"
0: Normal operation
1 SD Preset 1: Force signal detect "on"
0: Normal operation
0 Reserved Set bit to 0.
0x23 CH3 - CHB3
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0.
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2 RXDET Yes 00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0 Reserved Set bits to 0.
0x24 CH3 - CHB3
EQ		 7:0 EQ Control R/W 0x2F Yes IB3 EQ Control - total of 256 levels.
See Table 2.
0x25 CH3 - CHB3
VOD 		7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 MODE_SEL Yes 1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3 Reserved Yes Set bits to default value - 101.
2:0 VOD Control Yes OB0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x26 CH3 - CHB3
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH3 - CHB3.
1: RX = detected
0: RX = not detected
6:5 MODE_DET STATUS R Observation bit for MODE_DET CH3 - CHB3.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W Yes OB3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x27 CH3 - CHB3
IDLE Threshold		 7:4 Reserved R/W 0x00 Set bits to 0.
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0 IDLE thd Yes De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x28 Signal Detect Control 7:6 Reserved R/W 0x0C Set bits to 0.
5:4 High IDLE Yes Enable higher range of Signal Detect Thresholds
[5]: CH0 - CH3
[4]: CH4 -CH7
3:2 Fast IDLE Yes Enable Fast OOB response
[3]: CH0 - CH3
[2]: CH4 -CH7
1:0 Reduced SD Gain Yes Enable reduced Signal Detect Gain
[1]: CH0 - CH3
[0]: CH4 -CH7
0x29 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x2A CH4 - CHA0
Signal Detect		 7:3 Reserved R/W 0x00 Set bits to 0.
2 SD Reset 1: Force signal detect "off"
0: Normal operation
1 SD Preset 1: Force signal detect "on"
0: Normal operation
0 Reserved Set bit to 0.
0x2B CH4 - CHA0
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0.
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2 RXDET Yes 00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0 Reserved Set bits to 0.
0x2C CH4 - CHA0
EQ		 7:0 EQ Control R/W 0x2F Yes IA0 EQ Control - total of 256 levels.
See Table 2.
0x2D CH4 - CHA0
VOD 		7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 MODE_SEL Yes 1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3 Reserved Yes Set bits to default value - 101.
2:0 VOD Control Yes OA0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x2E CH4 - CHA0
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH4 - CHA0.
1: RX = detected
0: RX = not detected
6:5 MODE_DET STATUS R Observation bit for MODE_DET CH4 - CHA0.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W Yes OA0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x2F CH4 - CHA0
IDLE Threshold		 7:4 Reserved R/W 0x00 Set bits to 0.
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0 IDLE thd Yes De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x30 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x31 CH5 - CHA1
Signal Detect		 7:3 Reserved R/W 0x00 Set bits to 0.
2 SD Reset 1: Force signal detect "off"
0: Normal operation
1 SD Preset 1: Force signal detect "on"
0: Normal operation
0 Reserved Set bit to 0.
0x32 CH5 - CHA1
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0.
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2 RXDET Yes 00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0 Reserved Set bits to 0.
0x33 CH5 - CHA1
EQ		 7:0 EQ Control R/W 0x2F Yes IA1 EQ Control - total of 256 levels.
See Table 2.
0x34 CH5 - CHA1
VOD 		7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 MODE_SEL Yes 1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3 Reserved Yes Set bits to default value - 101.
2:0 VOD Control Yes OA1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x35 CH5 - CHA1
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH5 - CHA1.
1: RX = detected
0: RX = not detected
6:5 MODE_DET STATUS R Observation bit for MODE_DET CH5 - CHA1.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W Yes OA1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x36 CH5 - CHA1
IDLE Threshold		 7:4 Reserved R/W 0x00 Set bits to 0.
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0 IDLE thd Yes De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x37 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x38 CH6 - CHA2
Signal Detect		 7:3 Reserved R/W 0x00 Set bits to 0.
2 SD Reset 1: Force signal detect "off"
0: Normal operation
1 SD Preset 1: Force signal detect "on"
0: Normal operation
0 Reserved Set bit to 0.
0x39 CH6 - CHA2
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0.
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2 RXDET Yes 00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0 Reserved Set bits to 0.
0x3A CH6 - CHA2
EQ		 7:0 EQ Control R/W 0x2F Yes IA2 EQ Control - total of 256 levels.
See Table 2.
0x3B CH6 - CHA2
VOD 		7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 MODE_SEL Yes 1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3 Reserved Yes Set bits to default value - 101.
2:0 VOD Control Yes OA2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x3C CH6 - CHA2
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH6 - CHA2.
1: RX = detected
0: RX = not detected
6:5 MODE_DET STATUS R Observation bit for MODE_DET CH6 - CHA2.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W Yes OA2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x3D CH6 - CHA2
IDLE Threshold		 7:4 Reserved R/W 0x00 Set bits to 0.
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0 IDLE thd Yes De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x3E Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x3F CH0 - CHB0
Signal Detect		 7:3 Reserved R/W 0x00 Set bits to 0.
2 SD Reset 1: Force signal detect "off"
0: Normal operation
1 SD Preset 1: Force signal detect "on"
0: Normal operation
0 Reserved Set bit to 0.
0x40 CH7 - CHA3
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0.
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: override IDLE control.
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: override IDLE control.
3:2 RXDET Yes 00: Input is high-z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is high-z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is high-z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin.
1:0 Reserved Set bits to 0.
0x41 CH7 - CHA3
EQ		 7:0 EQ Control R/W 0x2F Yes IA3 EQ Control - total of 256 levels.
See Table 2.
0x42 CH7 - CHA3
VOD 		7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 MODE_SEL Yes 1: PCIe Gen-1 or PCIe Gen-2
0: PCIe Gen-3
Note: override the MODE pin.
5:3 Reserved Yes Set bits to default value - 101.
2:0 VOD Control Yes OA3 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x43 CH7 - CHA3
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH7 - CHA3.
1: RX = detected
0: RX = not detected
6:5 MODE_DET STATUS R Observation bit for MODE_DET CH7 - CHA3.
00: PCIe Gen-1 (2.5G)
01: PCIe Gen-2 (5G)
11: PCIe Gen-3 (8G+)
Note: Only functions when MODE Pin = Automatic
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W Yes OA3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x44 CH7 - CHA3
IDLE Threshold		 7:4 Reserved R/W 0x00 Set bits to 0.
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: override the SD_TH pin.
1:0 IDLE thd Yes De-Assert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: override the SD_TH pin.
0x45 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x46 Reserved 7:0 Reserved R/W 0x38 Set bits to 0x38
0x47 Reserved 7:4 Reserved R/W 0x00 Set bits to 0
3:0 Reserved R/W Yes Set bits to 0
0x48 Reserved 7:6 Reserved R/W 0x05 Yes Set bits to 0
5:0 Reserved R/W Set bits to 00 0101'b
0x49 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4A Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4B Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4C Reserved 7:3 Reserved R/W 0x00 Yes Set bits to 0
2:1 Reserved R/W Set bits to 0
0 Reserved R/W Yes Set bits to 0
0x4D Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4E Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4F Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x50 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x51 Device ID 7:5 VERSION R 0x45 010'b
4:0 ID 00101'b
0x52 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x53 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x54 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x55 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x56 Reserved 7:0 Reserved R/W 0x10 Set bits to 0x10
0x57 Reserved 7:0 Reserved R/W 0x64 Set bits to 0x64
0x58 Reserved 7:0 Reserved R/W 0x21 Set bits to 0x21
0x59 Reserved 7:1 Reserved R/W 0x00 Set bits to 0
0 Reserved Yes Set bit to 0
0x5A Reserved 7:0 Reserved R/W 0x54 Yes Set bits to 0x54
0x5B Reserved 7:0 Reserved R/W 0x54 Yes Set bits to 0x54
0x5C Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x5D Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x5E Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x5F Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x60 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x61 Reserved 7:0 Reserved R/W 0x00 Set bits to 0