SNLS426F August   2012  – November 2018 DS125BR800

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Description (cont.)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics: Serial Management Bus Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
      2. 8.3.2 PCIe Signal Integrity
        1. 8.3.2.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
          1. 8.3.2.1.1 Signal Detect Control for Datarates above 8 Gbps
        2. 8.3.2.2 MODE Operation with SMBus Registers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Mode
    5. 8.5 Programming
      1. 8.5.1 SMBus Master Mode
      2. 8.5.2 Transfer of Data Via the SMBus
      3. 8.5.3 System Management Bus (SMBus) and Configuration Registers
      4. 8.5.4 SMBus Transactions
      5. 8.5.5 Writing a Register
      6. 8.5.6 Reading a Register
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.1 SMBus Master Mode

The DS125BR800 devices support reading directly from an external EEPROM device by implementing SMBus Master mode. When using the SMBus master mode, the DS125BR800 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific guidelines. For additional information, refer to SNLA228.

  • Set ENSMB = Float — enable the SMBUS master mode.
  • The external EEPROM device address byte must be 0xA0 and capable of 520 kHz operation at 2.5 V and 3.3 V supply.
  • Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.

When tying multiple DS125BR800 devices to the SDA and SCL bus, use these guidelines to configure the devices.

  • Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM. Example below is for 4 device.
    • U1: AD[3:0] = 0000 = 0xB0,
    • U2: AD[3:0] = 0001 = 0xB2,
    • U3: AD[3:0] = 0010 = 0xB4,
    • U4: AD[3:0] = 0011 = 0xB6
  • Use a pull-up resistor on SDA and SCL; value = 2 kΩ
  • Daisy-chain READ_EN (pin 26) and ALL_DONE (pin 27) from one device to the next device in the sequence so that they do not compete for the EEPROM at the same time.
    1. Tie READ_EN of the 1st device in the chain (U1) to GND
    2. Tie ALL_DONE of U1 to READ_EN of U2
    3. Tie ALL_DONE of U2 to READ_EN of U3
    4. Tie ALL_DONE of U3 to READ_EN of U4
    5. Optional: Tie ALL_DONE output of U4 to a LED to show the devices have been loaded successfully

Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS125BR800 device. The first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed pattern (8’hA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS125BR800 address and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM. There are 37 bytes of data size for each DS125BR800 device. For additional information on EEPROM programming, refer to SNLA228.

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:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8 :200020008005F5A800005454000000000000000000000000000000000000000000000000F6 :20006000000000000000000000000000000000000000000000000000000000000000000080 :20008000000000000000000000000000000000000000000000000000000000000000000060 :2000A000000000000000000000000000000000000000000000000000000000000000000040 :2000C000000000000000000000000000000000000000000000000000000000000000000020 :2000E000000000000000000000000000000000000000000000000000000000000000000000 :200040000000000000000000000000000000000000000000000000000000000000000000A0

NOTE

The maximum EEPROM size supported is 8-kbits (1024 x 8 bits).

Table 7. EEPROM Register Map - Single Device with Default Value

EEPROM Address Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BIt 0
Description 0x00 CRC EN Address Map Present EEPROM > 256 Bytes Reserved DEVICE COUNT[3] DEVICE COUNT[2] DEVICE COUNT[1] DEVICE COUNT[0]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x01 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x02 Max EEPROM Burst size[7] Max EEPROM Burst size[6] Max EEPROM Burst size[5] Max EEPROM Burst size[4] Max EEPROM Burst size[3] Max EEPROM Burst size[2] Max EEPROM Burst size[1] Max EEPROM Burst size[0]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x03 PWDN_ch7 PWDN_ch6 PWDN_ch5 PWDN_ch4 PWDN_ch3 PWDN_ch2 PWDN_ch1 PWDN_ch0
SMBus Register 0x01 [7] 0x01 [6] 0x01 [5] 0x01 [4] 0x01 [3] 0x01 [2] 0x01 [1] 0x01 [0]
Default Value 0x00 0 0 0 0 0 0 0 0
Description 0x04 lpbk_1 lpbk_0 PWDN_INPUTS PWDN_OSC Ovrd_PWDN Reserved Reserved Reserved
SMBus Register 0x02 [5] 0x02 [4] 0x02 [3] 0x02 [2] 0x02 [0] 0x04 [7] 0x04 [6] 0x04 [5]
Default Value 00 0 0 0 0 0 0 0 0
Description 0x05 Reserved Reserved Reserved Reserved Reserved rxdet_btb_en Ovrd_idle_th Ovrd_RES
SMBus Register 0x04 [4] 0x04 [3] 0x04 [2] 0x04 [1] 0x04 [0] 0x06 [4] 0x08 [6] 0x08 [5]
Default Value 04 0 0 0 0 0 1 0 0
Description 0x06 Ovrd_IDLE Ovrd_RX_DET Ovrd_MODE Ovrd_RES Ovrd_RES rx_delay_sel_2 rx_delay_sel_1 rx_delay_sel_0
SMBus Register 0x08 [4] 0x08 [3] 0x08 [2] 0x08 [1] 0x08 [0] 0x0B [6] 0x0B [5] 0x0B [4]
Default Value 07 0 0 0 0 0 1 1 1
Description 0x07 RD_delay_sel_3 RD_delay_sel_2 RD_delay_sel_1 RD_delay_sel_0 ch0_Idle_auto ch0_Idle_sel ch0_RXDET_1 ch0_RXDET_0
SMBus Register 0x0B [3] 0x0B [2] 0x0B [1] 0x0B [0] 0x0E [5] 0x0E [4] 0x0E [3] 0x0E [2]
Default Value 00 0 0 0 0 0 0 0 0
Description 0x08 ch0_BST_7 ch0_BST_6 ch0_BST_5 ch0_BST_4 ch0_BST_3 ch0_BST_2 ch0_BST_1 ch0_BST_0
SMBus Register 0x0F [7] 0x0F [6] 0x0F [5] 0x0F [4] 0x0F [3] 0x0F [2] 0x0F [1] 0x0F [0]
Default Value 2F 0 0 1 0 1 1 1 1
Description 0x09 ch0_Sel_scp ch0_Sel_mode ch0_RES_2 ch0_RES_1 ch0_RES_0 ch0_VOD_2 ch0_VOD_1 ch0_VOD_0
SMBus Register 0x10 [7] 0x10 [6] 0x10 [5] 0x10 [4] 0x10 [3] 0x10 [2] 0x10 [1] 0x10 [0]
Default Value AD 1 0 1 0 1 1 0 1
Description 0x0A ch0_DEM_2 ch0_DEM_1 ch0_DEM_0 ch0_Slow ch0_idle_tha_1 ch0_idle_tha_0 ch0_idle_thd_1 ch0_idle_thd_0
SMBus Register 0x11 [2] 0x11 [1] 0x11 [0] 0x12 [7] 0x12 [3] 0x12 [2] 0x12 [1] 0x12 [0]
Default Value 40 0 1 0 0 0 0 0 0
Description 0x0B ch1_Idle_auto ch1_Idle_sel ch1_RXDET_1 ch1_RXDET_0 ch1_BST_7 ch1_BST_6 ch1_BST_5 ch1_BST_4
SMBus Register 0x15 [5] 0x15 [4] 0x15 [3] 0x15 [2] 0x16 [7] 0x16 [6] 0x16 [5] 0x16 [4]
Default Value 02 0 0 0 0 0 0 1 0
Description 0x0C ch1_BST_3 ch1_BST_2 ch1_BST_1 ch1_BST_0 ch1_Sel_scp ch1_Sel_mode ch1_RES_2 ch1_RES_1
SMBus Register 0x16 [3] 0x16 [2] 0x16 [1] 0x16 [0] 0x17 [7] 0x17 [6] 0x17 [5] 0x17 [4]
Default Value FA 1 1 1 1 1 0 1 0
Description 0x0D ch1_RES_0 ch1_VOD_2 ch1_VOD_1 ch1_VOD_0 ch1_DEM_2 ch1_DEM_1 ch1_DEM_0 ch1_Slow
SMBus Register 0x17 [3] 0x17 [2] 0x17 [1] 0x17 [0] 0x18 [2] 0x18 [1] 0x18 [0] 0x19 [7]
Default Value 2F 1 1 0 1 0 1 0 0
Description 0x0E ch1_idle_tha_1 ch1_idle_tha_0 ch1_idle_thd_1 ch1_idle_thd_0 ch2_Idle_auto ch2_Idle_sel ch2_RXDET_1 ch2_RXDET_0
SMBus Register 0x19 [3] 0x19 [2] 0x19 [1] 0x19 [0] 0x1C [5] 0x1C [4] 0x1C [3] 0x1C [2]
Default Value 00 0 0 0 0 0 0 0 0
Description 0x0F ch2_BST_7 ch2_BST_6 ch2_BST_5 ch2_BST_4 ch2_BST_3 ch2_BST_2 ch2_BST_1 ch2_BST_0
SMBus Register 0x1D [7] 0x1D [6] 0x1D [5] 0x1D [4] 0x1D [3] 0x1D [2] 0x1D [1] 0x1D [0]
Default Value 2F 0 0 1 0 1 1 1 1
Description 0x10 ch2_Sel_scp ch2_Sel_mode ch2_RES_2 ch2_RES_1 ch2_RES_0 ch2_VOD_2 ch2_VOD_1 ch2_VOD_0
SMBus Register 0x1E [7] 0x1E [6] 0x1E [5] 0x1E [4] 0x1E [3] 0x1E [2] 0x1E [1] 0x1E [0]
Default Value AD 1 0 1 0 1 1 0 1
Description 0x11 ch2_DEM_2 ch2_DEM_1 ch2_DEM_0 ch2_Slow ch2_idle_tha_1 ch2_idle_tha_0 ch2_idle_thd_1 ch2_idle_thd_0
SMBus Register 0x1F [2] 0x1F [1] 0x1F [0] 0x20 [7] 0x20 [3] 0x20 [2] 0x20 [1] 0x20 [0]
Default Value 40 0 1 0 0 0 0 0 0
Description 0x12 ch3_Idle_auto ch3_Idle_sel ch3_RXDET_1 ch3_RXDET_0 ch3_BST_7 ch3_BST_6 ch3_BST_5 ch3_BST_4
SMBus Register 0x23 [5] 0x23 [4] 0x23 [3] 0x23 [2] 0x24 [7] 0x24 [6] 0x24 [5] 0x24 [4]
Default Value 02 0 0 0 0 0 0 1 0
Description 0x13 ch3_BST_3 ch3_BST_2 ch3_BST_1 ch3_BST_0 ch3_Sel_scp ch3_Sel_mode ch3_RES_2 ch3_RES_1
SMBus Register 0x24 [3] 0x24 [2] 0x24 [1] 0x24 [0] 0x25 [7] 0x25 [6] 0x25 [5] 0x25 [4]
Default Value FA 1 1 1 1 1 0 1 0
Description 0x14 ch3_RES_0 ch3_VOD_2 ch3_VOD_1 ch3_VOD_0 ch3_DEM_2 ch3_DEM_1 ch3_DEM_0 ch3_Slow
SMBus Register 0x25 [3] 0x25 [2] 0x25 [1] 0x25 [0] 0x26 [2] 0x26 [1] 0x26 [0] 0x27 [7]
Default Value D4 1 1 0 1 0 1 0 0
Description 0x15 ch3_idle_tha_1 ch3_idle_tha_0 ch3_idle_thd_1 ch3_idle_thd_0 ovrd_fast_idle en_high_idle_th_n en_high_idle_th_s en_fast_idle_n
SMBus Register 0x27 [3] 0x27 [2] 0x27 [1] 0x27 [0] 0x28 [6] 0x28 [5] 0x28 [4] 0x28 [3]
Default Value 09 0 0 0 0 0 0 0 1
Description 0x16 en_fast_idle_s eqsd_mgain_n eqsd_mgain_s ch4_Idle_auto ch4_Idle_sel ch4_RXDET_1 ch4_RXDET_0 ch4_BST_7
SMBus Register 0x28 [2] 0x28 [1] 0x28 [0] 0x2B [5] 0x2B [4] 0x2B [3] 0x2B [2] 0x2C [7]
Default Value 80 1 0 0 0 0 0 0 0
Description 0x17 ch4_BST_6 ch4_BST_5 ch4_BST_4 ch4_BST_3 ch4_BST_2 ch4_BST_1 ch4_BST_0 ch4_Sel_scp
SMBus Register 0x2C [6] 0x2C [5] 0x2C [4] 0x2C [3] 0x2C [2] 0x2C [1] 0x2C [0] 0x2D [7]
Default Value 5F 0 1 0 1 1 1 1 1
Description 0x18 ch4_Sel_mode ch4_RES_2 ch4_RES_1 ch4_RES_0 ch4_VOD_2 ch4_VOD_1 ch4_VOD_0 ch4_DEM_2
SMBus Register 0x2D [6] 0x2D [5] 0x2D [4] 0x2D [3] 0x2D [2] 0x2D [1] 0x2D [0] 0x2E [2]
Default Value 5A 0 1 0 1 1 0 1 0
Description 0x19 ch4_DEM_1 ch4_DEM_0 ch4_Slow ch4_idle_tha_1 ch4_idle_tha_0 ch4_idle_thd_1 ch4_idle_thd_0 ch5_Idle_auto
SMBus Register 0x2E [1] 0x2E [0] 0x2F [7] 0x2F [3] 0x2F [2] 0x2F [1] 0x2F [0] 0x32 [5]
Default Value 80 1 0 0 0 0 0 0 0
Description 0x1A ch5_Idle_sel ch5_RXDET_1 ch5_RXDET_0 ch5_BST_7 ch5_BST_6 ch5_BST_5 ch5_BST_4 ch5_BST_3
SMBus Register 0x32 [4] 0x32 [3] 0x32 [2] 0x33 [7] 0x33 [6] 0x33 [5] 0x33 [4] 0x33 [3]
Default Value 05 0 0 0 0 0 1 0 1
Description 0x1B ch5_BST_2 ch5_BST_1 ch5_BST_0 ch5_Sel_scp ch5_Sel_mode ch5_RES_2 ch5_RES_1 ch5_RES_0
SMBus Register 0x33 [2] 0x33 [1] 0x33 [0] 0x34 [7] 0x34 [6] 0x34 [5] 0x34 [4] 0x34 [3]
Default Value F5 1 1 1 1 0 1 0 1
Description 0x1C ch5_VOD_2 ch5_VOD_1 ch5_VOD_0 ch5_DEM_2 ch5_DEM_1 ch5_DEM_0 ch5_Slow ch5_idle_tha_1
SMBus Register 0x34 [2] 0x34 [1] 0x34 [0] 0x35 [2] 0x35 [1] 0x35 [0] 0x36 [7] 0x36 [3]
Default Value A8 1 0 1 0 1 0 0 0
Description 0x1D ch5_idle_tha_0 ch5_idle_thd_1 ch5_idle_thd_0 ch6_Idle_auto ch6_Idle_sel ch6_RXDET_1 ch6_RXDET_0 ch6_BST_7
SMBus Register 0x36 [2] 0x36 [1] 0x36 [0] 0x39 [5] 0x39 [4] 0x39 [3] 0x39 [2] 0x3A [7]
Default Value 00 0 0 0 0 0 0 0 0
Description 0x1E ch6_BST_6 ch6_BST_5 ch6_BST_4 ch6_BST_3 ch6_BST_2 ch6_BST_1 ch6_BST_0 ch6_Sel_scp
SMBus Register 0x3A [6] 0x3A [5] 0x3A [4] 0x3A [3] 0x3A [2] 0x3A [1] 0x3A [0] 0x3B [7]
Default Value 5F 0 1 0 1 1 1 1 1
Description 0x1F ch6_Sel_mode ch6_RES_2 ch6_RES_1 ch6_RES_0 ch6_VOD_2 ch6_VOD_1 ch6_VOD_0 ch6_DEM_2
SMBus Register 0x3B [6] 0x3B [5] 0x3B [4] 0x3B [3] 0x3B [2] 0x3B [1] 0x3B [0] 0x3C [2]
Default Value 5A 0 1 0 1 1 0 1 0
Description 0x20 ch6_DEM_1 ch6_DEM_0 ch6_Slow ch6_idle_tha_1 ch6_idle_tha_0 ch6_idle_thd_1 ch6_idle_thd_0 ch7_Idle_auto
SMBus Register 0x3C [1] 0x3C [0] 0x3D [7] 0x3D [3] 0x3D [2] 0x3D [1] 0x3D [0] 0x40 [5]
Default Value 80 1 0 0 0 0 0 0 0
Description 0x21 ch7_Idle_sel ch7_RXDET_1 ch7_RXDET_0 ch7_BST_7 ch7_BST_6 ch7_BST_5 ch7_BST_4 ch7_BST_3
SMBus Register 0x40 [4] 0x40 [3] 0x40 [2] 0x41 [7] 0x41 [6] 0x41 [5] 0x41 [4] 0x41 [3]
Default Value 05 0 0 0 0 0 1 0 1
Description 0x22 ch7_BST_2 ch7_BST_1 ch7_BST_0 ch7_Sel_scp ch7_Sel_mode ch7_RES_2 ch7_RES_1 ch7_RES_0
SMBus Register 0x41 [2] 0x41 [1] 0x41 [0] 0x42 [7] 0x42 [6] 0x42 [5] 0x42 [4] 0x42 [3]
Default Value F5 1 1 1 1 0 1 0 1
Description 0x23 ch7_VOD_2 ch7_VOD_1 ch7_VOD_0 ch7_DEM_2 ch7_DEM_1 ch7_DEM_0 ch7_Slow ch7_idle_tha_1
SMBus Register 0x42 [2] 0x42 [1] 0x42 [0] 0x43 [2] 0x43 [1] 0x43 [0] 0x44 [7] 0x44 [3]
Default Value A8 1 0 1 0 1 0 0 0
Description 0x24 ch7_idle_tha_0 ch7_idle_thd_1 ch7_idle_thd_0 Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x44 [2] 0x44 [1] 0x44 [0] 0x47 [3] 0x47 [2] 0x47 [2] 0x47 [0] 0x48 [7]
Default Value 00 0 0 0 0 0 0 0 0
Description 0x25 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x48 [6] 0x4C [7] 0x4C [6] 0x4C [5] 0x4C [4] 0x4C [3] 0x4C [0] 0x59 [0]
Default Value 00 0 0 0 0 0 0 0 0
Description 0x26 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x5A [7] 0x5A [6] 0x5A [5] 0x5A [4] 0x5A [3] 0x5A [2] 0x5A [1] 0x5A [0]
Default Value 54 0 1 0 1 0 1 0 0
Description 0x27 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Register 0x5B [7] 0x5B [6] 0x5B [5] 0x5B [4] 0x5B [3] 0x5B [2] 0x5B [1] 0x5B [0]
Default Value 54 0 1 0 1 0 1 0 0

Table 8. Example of EEPROM for Four Devices Using Two Address Maps

EEPROM Address Address (Hex) EEPROM Data Comments
0 00 0x43 CRC_EN = 0, Address Map = 1, >256 bytes = 0, Device Count[3:0] = 3
1 01 0x00
2 02 0x08 EEPROM Burst Size
3 03 0x00 CRC not used
4 04 0x0B Device 0 Address Location
5 05 0x00 CRC not used
6 06 0x0B Device 1 Address Location
7 07 0x00 CRC not used
8 08 0x30 Device 2 Address Location
9 09 0x00 CRC not used
10 0A 0x30 Device 3 Address Location
11 0B 0x00 Begin Device 0, 1 - Address Offset 3
12 0C 0x00
13 0D 0x04
14 0E 0x07
15 0F 0x00
16 10 0x00 EQ CHB0 = 00
17 11 0xAB VOD CHB0 = 1.0 V
18 12 0x00 DEM CHB0 = 0 (0 dB)
19 13 0x00 EQ CHB1 = 00
20 14 0x0A VOD CHB1 = 1.0 V
21 15 0xB0 DEM CHB1 = 0 (0 dB)
22 16 0x00
23 17 0x00 EQ CHB2 = 00
24 18 0xAB VOD CHB2 = 1.0 V
25 19 0x00 DEM CHB2 = 0 (0 dB)
26 1A 0x00 EQ CHB3 = 00
27 1B 0x0A VOD CHB3 = 1.0 V
28 1C 0xB0 DEM CHB3 = 0 (0 dB)
29 1D 0x01
30 1E 0x80
31 1F 0x01 EQ CHA0 = 00
32 20 0x56 VOD CHA0 = 1.0 V
33 21 0x00 DEM CHA0 = 0 (0 dB)
34 22 0x00 EQ CHA1 = 00
35 23 0x15 VOD CHA1 = 1.0 V
36 24 0x60 DEM CHA1 = 0 (0 dB)
37 25 0x00
38 26 0x01 EQ CHA2 = 00
39 27 0x56 VOD CHA2 = 1.0 V
40 28 0x00 DEM CHA2 = 0 (0 dB)
41 29 0x00 EQ CHA3 = 00
42 2A 0x15 VOD CHA3 = 1.0 V
43 2B 0x60 DEM CHA3 = 0 (0 dB)
44 2C 0x00
45 2D 0x00
46 2E 0x54
47 2F 0x54 End Device 0, 1 - Address Offset 39
48 30 0x00 Begin Device 2, 3 - Address Offset 3
49 31 0x00
50 32 0x04
51 33 0x07
52 34 0x00
53 35 0x00 EQ CHB0 = 00
54 36 0xAB VOD CHB0 = 1.0 V
55 37 0x00 DEM CHB0 = 0 (0 dB)
56 38 0x00 EQ CHB1 = 00
57 39 0x0A VOD CHB1 = 1.0 V
58 3A 0xB0 DEM CHB1 = 0 (0 dB)
59 3B 0x00
60 3C 0x00 EQ CHB2 = 00
61 3D 0xAB VOD CHB2 = 1.0 V
62 3E 0x00 DEM CHB2 = 0 (0 dB)
63 3F 0x00 EQ CHB3 = 00
64 40 0x0A VOD CHB3 = 1.0 V
65 41 0xB0 DEM CHB3 = 0 (0 dB)
66 42 0x01
67 43 0x80
68 44 0x01 EQ CHA0 = 00
69 45 0x56 VOD CHA0 = 1.0 V
70 46 0x00 DEM CHA0 = 0 (0 dB)
71 47 0x00 EQ CHA1 = 00
72 48 0x15 VOD CHA1 = 1.0 V
73 49 0x60 DEM CHA1 = 0 (0 dB)
74 4A 0x00
75 4B 0x01 EQ CHA2 = 00
76 4C 0x56 VOD CHA2 = 1.0 V
77 4D 0x00 DEM CHA2 = 0 (0 dB)
78 4E 0x00 EQ CHA3 = 00
79 4F 0x15 VOD CHA3 = 1.0 V
80 50 0x60 DEM CHA3 = 0 (0 dB)
81 51 0x00
82 52 0x00
83 53 0x54
84 54 0x54 End Device 2, 3 - Address Offset 39

NOTE: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. This example has all 8 channels set to EQ = 00 (min boost), VOD = 1.0 V, DEM = 0 (0 dB) and multiple device can point to the same address map. Maximum EEPROM size is 8kbits (1024 x 8-bits).