SNLS346C August   2011  – June 2014 DS90UR903Q-Q1 , DS90UR904Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing for PCLK
    7. 6.7  Serial Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (See )
    8. 6.8  Serial Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
    9. 6.9  Serializer Switching Characteristics
    10. 6.10 Deserializer Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Typical Application Diagram
      2. 7.2.2 Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Signal Quality Enhancers
        1. 7.3.2.1 Des - Receiver Input Equalization (EQ)
      3. 7.3.3 Emi Reduction
        1. 7.3.3.1 Des - Receiver Staggered Output
        2. 7.3.3.2 Des Spread Spectrum Clocking
    4. 7.4 Device Functional Modes
      1. 7.4.1 LVCMOS VDDIO Option
      2. 7.4.2 Powerdown
      3. 7.4.3 Pixel Clock Edge Select (TRFB/RRFB)
    5. 7.5 Programming
      1. 7.5.1 Description of Serial Control Bus
      2. 7.5.2 ID[X] Address Decoder
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Typical Application Connection
        2. 8.2.2.2 AC Coupling
        3. 8.2.2.3 Power Up Requirements and PDB PIN
        4. 8.2.2.4 Transmission Media
        5. 8.2.2.5 Serial Interconnect Guidelines
        6. 8.2.2.6 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

40 Pin Serializer – DS90UR903Q
Package RTA
Top View
30164619.gif

DS90UR903Q Serializer Pin Functions

PIN I/O, TYPE DESCRIPTION
NAME NUMBER
LVCMOS PARALLEL INTERFACE
DIN[20:0] 5, 4, 3, 2, 1, 40, 39, 38, 37, 36, 35, 33, 32, 30, 29, 28, 27, 26, 25, 24, 23 Inputs, LVCMOS
w/ pull down		 Parallel data inputs.
PCLK 6 Input, LVCMOS
w/ pull down		 Pixel Clock Input Pin. Strobe edge set by TRFB control register.
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL 7 Input,
Open Drain		 Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA 8 Input/Output,
Open Drain		 Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
MODE 12 Input, LVCMOS
w/ pull down		 I2C Mode select
MODE = H, -REQUIRED. The MODE pin must be set HIGH to allow I2C configuration of the serializer.
ID[x] 9 Input, analog Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 1
CONTROL AND CONFIGURATION
PDB 13 Input, LVCMOS
w/ pull down		 Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down, the PLL is shutdown, and IDD is minimized. Programmed control register data are NOT retained and reset to default values
RES 10, 11 Input, LVCMOS
w/ pull down		 Reserved.
This pin MUST be tied LOW.
NC 22, 21, 20, 19 No Connect
FPD-LINK II INTERFACE
DOUT+ 17 Output, CML Non-inverting differential output. The interconnect must be AC Coupled with a 100 nF capacitor.
DOUT- 16 Output, CML Inverting differential output. The interconnect must be AC Coupled with a 100 nF capacitor.
POWER AND GROUND(1)
VDDPLL 14 Power, Analog PLL Power, 1.8V ±5%
VDDT 15 Power, Analog Tx Analog Power, 1.8V ±5%
VDDCML 18 Power, Analog CML Power, 1.8V ±5%
VDDD 34 Power, Digital Digital Power, 1.8V ±5%
VDDIO 31 Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VSS DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias.
48 Pin Deserializer - DS90UR904Q
Package RHS
Top View
30164620.gif

DS90UR904Q Deserializer Pin Descriptions

PIN I/O, TYPE DESCRIPTION
NAME NUMBER
LVCMOS PARALLEL INTERFACE
ROUT[20:0] 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28 Outputs, LVCMOS Parallel data outputs.
PCLK 4 Output, LVCMOS Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL 2 Input,
Open Drain		 Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA 1 Input/Output,
Open Drain		 Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
MODE 47 Input, LVCMOS
w/ pull up		 I2C Mode select
MODE = H -REQUIRED. The MODE pin must be set HIGH to allow I2C configuration of the deserializer.
ID[x] 9 Input, analog Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 2
CONTROL AND CONFIGURATION
PDB 35 Input, LVCMOS
w/ pull down		 Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power Down. Programmed control register data are NOT retained and reset to default values.
LOCK 34 Output,
LVCMOS		 LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by OSS_SEL control register. May be used as Link Status.
RES 37, 38, 39, 43, 44, 46 - Reserved.
Pin 46: This pin MUST be tied LOW.
Pin 37, 43, 44: Leave pin open.
Pins 38, 39: Route to test point or leave open if unused.
NC 30, 31, 32, 33 No Connect
FPD-LINK II INTERFACE
RIN+ 41 Input, CML Noninverting differential input. The interconnect must be AC Coupled with a 100 nF capacitor.
RIN- 42 Inputt, CML Inverting differential input. The interconnect must be AC Coupled with a 100 nF capacitor.
POWER AND GROUND (1)
VDDSSCG 3 Power, Digital SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
VDDIO1/2/3 29, 20, 7 Power, Digital LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDD 17 Power, Digital Digital Core Power, 1.8V ±5%
VDDR 36 Power, Analog Rx Analog Power, 1.8V ±5%
VDDCML 40 Power, Analog 1.8V ±5%
VDDPLL 45 Power, Analog PLL Power, 1.8V ±5%
VSS DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias.