SLPS730B august   2021  – august 2023 JFE2140

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 AC Measurement Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precision Matching
      2. 8.3.2 Ultra-Low Noise
      3. 8.3.3 Low Gate Current
      4. 8.3.4 Input Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Protection Diodes
      2. 9.1.2 Cascode Configuration
      3. 9.1.3 Common-Source Amplifier
      4. 9.1.4 Composite Amplifiers
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Noise, Low-Power, High-Input-Impedance Composite Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Front-End Design
        1. 9.2.2.1 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 10.1.1.3 TI Reference Designs
        4. 10.1.1.4 Filter Design Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Typical Characteristics

at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 10 V (unless otherwise noted)

GUID-20210810-SS0I-GWVG-6ZGJ-QSHRXL6DNX3R-low.png
 
Figure 6-1 Drain-to-Source Current vs Gate-to-Source Voltage
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Figure 6-3 Drain-to-Source Current vs Drain-to-Source Voltage
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Figure 6-5 Common Source Transconductance vs Drain‑to‑Source Voltage
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 VDS = 5 V
Figure 6-7 Gate Current vs Gate-to-Source Voltage
GUID-20210810-SS0I-PDFZ-8V1J-ZGMWTRNG1TQV-low.png
 
Figure 6-9 IDSS vs Drain-to-Source Voltage
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VGS(Ch.1) – VGS(Ch.2)  VDS = 5 V 5 Units
Figure 6-11 VGS Mismatch vs Drain-to-Source Current
GUID-20210813-SS0I-JWNV-W9KS-KHZZH5HWCFHR-low.png
VGS(Ch.1) – VGS(Ch.2)  
Figure 6-13 VGS Mismatch vs VDS
GUID-20210812-SS0I-JVS4-MTQQ-XRNBS18BCZGB-low.png
f = 1 kHz
Figure 6-15 Noise Density Contributors vs Input Gate Resistance
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Figure 6-17 Input, Output, and Reverse Transfer Capacitance vs Drain-to-Source Voltage
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Figure 6-2 Drain-to-Source Current vs Drain-to-Source Voltage
GUID-20210810-SS0I-8FVJ-22TD-G5M035KVFMSP-low.png
 
Figure 6-4 Common Source Transconductance vs Drain‑to‑Source Current
GUID-20210810-SS0I-JGBX-0RDZ-T91RKPWW1DG7-low.png
 
Figure 6-6 Gate Current vs Drain-to-Source Voltage
GUID-20210810-SS0I-K2MH-WW6Z-BB1LMGBGVJB8-low.png
VDS = 5 V
Figure 6-8 Gate-to-Source Voltage vs Temperature
GUID-20210812-SS0I-1DSV-KQXS-QCZPGXMSXF70-low.png
 VGS(Ch.1) – VGS(Ch.2)  IDS = 2 mA
Figure 6-10 VGS Mismatch Histogram
GUID-20210812-SS0I-CLLR-K42V-KSFHKPPX0FR7-low.png
VGS(Ch.1) – VGS(Ch.2)   IDS = 2 mA 5 Units
Figure 6-12 VGS Mismatch vs Temperature
GUID-20210810-SS0I-KDMD-HQC3-XDSTKFDQ1JW9-low.png
 
Figure 6-14 Input-Referred Noise Density vs Frequency
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f = 1 kHz
Figure 6-16 Input-Referred Noise Spectral Density vs Drain‑to‑Source Current