SNVSB54A May   2018  – November 2018 LM5122ZA

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Lockout (UVLO)
      2. 7.3.2  High-Voltage VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  Slope Compensation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  PWM Comparator
      7. 7.3.7  Soft Start
      8. 7.3.8  HO and LO Drivers
      9. 7.3.9  Bypass Operation (VOUT = VIN)
      10. 7.3.10 Cycle-by-Cycle Current Limit
      11. 7.3.11 Clock Synchronization
      12. 7.3.12 Maximum Duty Cycle
      13. 7.3.13 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Control (Forced-PWM Mode and Diode-Emulation Mode)
      2. 7.4.2 MODE Control (Skip-Cycle Mode and Pulse-Skipping Mode)
      3. 7.4.3 Hiccup-Mode Overload Protection
      4. 7.4.4 Slave Mode and SYNCOUT
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Feedback Compensation
      2. 8.1.2 Sub-Harmonic Oscillation
      3. 8.1.3 Interleaved Boost Configuration
      4. 8.1.4 DCR Sensing
      5. 8.1.5 Output Overvoltage Protection
      6. 8.1.6 SEPIC Converter Simplified Schematic
      7. 8.1.7 Non-Isolated Synchronous Flyback Converter Simplified Schematic
      8. 8.1.8 Negative to Positive Conversion
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Timing Resistor RT
        2. 8.2.2.2  UVLO Divider RUV2, RUV1
        3. 8.2.2.3  Input Inductor LIN
        4. 8.2.2.4  Current Sense Resistor RS
        5. 8.2.2.5  Current Sense Filter RCSFP, RCSFN, CCS
        6. 8.2.2.6  Slope Compensation Resistor RSLOPE
        7. 8.2.2.7  Output Capacitor COUT
        8. 8.2.2.8  Input Capacitor CIN
        9. 8.2.2.9  VIN Filter RVIN, CVIN
        10. 8.2.2.10 Bootstrap Capacitor CBST and Boost Diode DBST
        11. 8.2.2.11 VCC Capacitor CVCC
        12. 8.2.2.12 Output Voltage Divider RFB1, RFB2
        13. 8.2.2.13 Soft-Start Capacitor CSS
        14. 8.2.2.14 Restart Capacitor CRES
        15. 8.2.2.15 Low-Side Power Switch QL
        16. 8.2.2.16 High-Side Power Switch QH and Additional Parallel Schottky Diode
        17. 8.2.2.17 Snubber Components
        18. 8.2.2.18 Loop Compensation Components CCOMP, RCOMP, CHF
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Sub-Harmonic Oscillation

Peak current mode regulator can exhibit unstable behavior when operating above 50% duty cycle. This behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin. Sub-harmonic oscillation can be prevented by adding an additional slope voltage ramp (slope compensation) on top of the sensed inductor current. By choosing K ≥ 0.82~1, the sub-harmonic oscillation is eliminated even with wide varying input voltage.

In time-domain analysis, the steady-state inductor current starting from an initial point returns to the same point. When the amplitude of an end cycle current error (dI1) caused by an initial perturbation (dI0) is less than the amplitude of dI0 or dI1/dI0 > –1, the perturbation naturally disappears after a few cycles. When dl1/dl0 < –1, the initial perturbation no longer disappear, it results in sub-harmonic oscillation in steady-state.

LM5122ZA Effect of Initial Pert.gifFigure 27. Effect of Initial Perturbation when dl1/dl0 < –1

dI1/dI0 can be calculated as:

Equation 19. LM5122ZA eq31_nvs954.gif

The relationship between dI1/dI0 and K factor is illustrated graphically in Figure 28.

LM5122ZA dl1 dl0 vs K.gifFigure 28. dl1/dl0 vs K Factor

The absolute minimum value of K is 0.5. When K < 0.5, the amplitude of dl1 is greater than the amplitude of dl0 and any initial perturbation results in sub-harmonic oscillation. If K = 1, any initial perturbation is removed in one switching cycle. This is known as one-cycle damping. When –1 < dl1/dl0 < 0, any initial perturbationis under-damped. Any perturbation is over-damped when 0 < dl1/dl0 < 1.

In the frequency-domain, Q, the quality factor of sampling gain term in modulator transfer function, is used to predict the tendency for sub-harmonic oscillation, which is defined as:

Equation 20. LM5122ZA eq32_nvs954.gif

The relationship between Q and K factor is shown in Figure 29.

LM5122ZA Sampling Gain Q vs K.gifFigure 29. Sampling Gain Q vs K Factor

The recommended absolute minimum value of K is 0.5. High gain peaking when K is less than 0.5 results sub-harmonic oscillation at fSW/2. A higher value of K factor may introduce additional phase shift near the crossover frequency, but has the benefit of reducing noise susceptibility in current loop. The maximum allowable value of K factor can be calculated by the maximum crossover frequency equation in frequency analysis formulas in Table 2.

Table 2. Boost Regulator Frequency Analysis

SIMPLIFIED FORMULA COMPREHENSIVE FORMULA(1)
MODULATOR TRANSER FUNCTION
LM5122ZA eq105_nvs954.gif
LM5122ZA eq37_nvs954.gif
Modulator DC gain (2)
LM5122ZA eq34_nvs954.gif
RHP zero (2)
LM5122ZA eq35_nvs954.gif
ESR zero
LM5122ZA eq36_nvs954.gif
LM5122ZA eq38_nvs954.gif
ESR pole Not considered
LM5122ZA eq39_nvs954.gif
Dominant load pole
LM5122ZA eq40_nvs954.gif
Sampled gain inductor pole Not considered
LM5122ZA eq41_nvs954.gif
or
LM5122ZA eq42_nvs954.gif
Quality factor Not considered
LM5122ZA eq43_nvs954.gif
Sub-harmonic double pole Not considered
LM5122ZA eq44_nvs954.gif

or

LM5122ZA eq45_nvs954.gif
K factor K = 1
LM5122ZA eq47_nvs954.gif
FEEDBACK TRANSFER FUNCTION
LM5122ZA eq48_nvs954.gif
Feedback DC gain
LM5122ZA eq49_nvs954.gif
Mid-band Gain
LM5122ZA eq50_nvs954.gif
Low frequency zero
LM5122ZA eq51_nvs954.gif
High frequency pole
LM5122ZA eq52_nvs954.gif
LM5122ZA eq96_nvs954.gif
OPEN LOOP RESPONSE
LM5122ZA eq54_nvs954.gif
LM5122ZA eq55_nvs954.gif
Crossover frequency (3)
(Open loop band width)
LM5122ZA eq56_nvs954.gif
Use graphic tool
Maximum cross over frequency(4)
LM5122ZA eq57_nvs954.gif
LM5122ZA eq58_nvs954.gif
or
LM5122ZA eq59_nvs954.gif
, whichever is smaller
Comprehensive equation includes an inductor pole and a gain peaking at fSW / 2, which is caused by sampling effect of the current mode control. Also, it assumes that a ceramic capacitor COUT2 (No ESR) is connected in parallel with COUT1. RESR1 represents ESR of COUT1.
With multiphase configuration, LM5122ZA eq60_nvs954.gif, LM5122ZA eq61_nvs954.gif, LM5122ZA eq62_nvs954.gif, and COUT = COUT of each phase x n, where n = number of phases. As is the current sense amplifier gain.
Assuming LM5122ZA eq64_nvs954.gif, LM5122ZA eq65_nvs954.gif, LM5122ZA eq66_nvs954.gif, LM5122ZA eq67_nvs954.gif, and LM5122ZA eq68_nvs954.gif.
The frequency at which 45° phase shift occurs in modulator phase characteristics.