SNOS674I October   1997  – February 2024 LMC6482 , LMC6484

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information LMC6482
    5. 5.5 Thermal Information LMC6484
    6. 5.6 Electrical Characteristics: VS = 5V
    7. 5.7 Electrical Characteristics: VS = 3V
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Amplifier Topology
      2. 6.3.2 Input Common-Mode Voltage Range
      3. 6.3.3 Rail-to-Rail Output
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Upgrading Applications
      2. 7.1.2 Data Acquisition Systems
      3. 7.1.3 Instrumentation Circuits
    2. 7.2 Typical Applications
      1. 7.2.1 3V Single-Supply Buffer Circuit
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Capacitive Load Compensation
          2. 7.2.1.2.2 Capacitive Load Tolerance
          3. 7.2.1.2.3 Compensating For Input Capacitance
          4. 7.2.1.2.4 Offset Voltage Adjustment
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Typical Single-Supply Applications
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Spice Macromodel
        2. 8.1.1.2 PSpice® for TI
        3. 8.1.1.3 TINA-TI™ Simulation Software (Free Download)
        4. 8.1.1.4 DIP-Adapter-EVM
        5. 8.1.1.5 DIYAMP-EVM
        6. 8.1.1.6 TI Reference Designs
        7. 8.1.1.7 Filter Design Tool
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • N|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision H (November 2023) to Revision I (February 2024)

  • Added LMC6484 and associated contentGo
  • Updated content from previous LMC6484 data sheet (SNOS675D) as detailed in Changes from Revision G (April 2020) to Revision H (November 2023) of this data sheet (SNOS674I)Go
  • Added values for LMC6482 and LMC6484 based on latest modeling standard to Thermal Information Go
  • Updated Electrical Characteristics format for LMC6484 and as detailed in Changes from Revision G (April 2020) to Revision H (November 2023) of this data sheetGo
  • Changed CMRR from 62dB to 60dB to match LMC6484 in Electrical Characteristics: VS = 5V Go
  • Updated footnote (2) on how slew rate minimum value is specified in Electrical Characteristics: VS = 5V Go
  • Changed THD from 0.01% to 0.02% in Electrical Characteristics: VS = 3V Go

Changes from Revision G (April 2020) to Revision H (November 2023)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Deleted specifications are typical, high voltage gain, and power good output from Features Go
  • Deleted M version device from data sheet; see the LMC6482QML for more informationGo
  • Updated front page figures in Description Go
  • Updated Pin Configuration and Functions Go
  • Added ± to input offset voltage, input offset voltage drift, input bias current, and input offset current in Electrical Characteristics Go
  • Updated parameter names throughout Electrical Characteristics for consistencyGo
  • Deleted notes 1, 2, and 3 from Electrical Characteristics Go
  • Changed supply current specification from total to per amplifier in Electrical Characteristics Go
  • Deleted Figure 11 to 13, Figure 19 to 23, Figure 32 to 33, and Figure 47 to 52Go
  • Updated functional block diagramGo
  • Updated description of the input stage in Amplifier Topology Go
  • Added Input Offset Voltage vs Common-Mode Voltage plot in Amplifier Topology Go
  • Updated the description in Rail-to-Rail Output Go
  • Added an improved instrumentation amplifier circuit to Instrumentation Circuits Go
  • Added Figure 7-7, Open-Loop Output Impedance and related content to Capacitive Load Compensation Go
  • Added OPA928 femtoampere-input bias-current op-amp recommendation to Typical Single-Supply Applications Go
  • Deleted references to the library disk in Spice Macromodel Go

Changes from Revision F (April 2020) to Revision G (April 2020)

  • Deleted old note 4 from Electrical Characteristics for V+ = 5 V tableGo

Changes from Revision E (April 2015) to Revision F (April 2020)

  • Changed junction temperature max value from –85°C to 85°C (typo) in Recommended Operating Conditions tableGo

Changes from Revision D (March 2013) to Revision E (April 2015)

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from Revision C (March 2013) to Revision D (March 2013)

  • Changed layout of National Semiconductor Data Sheet to TI formatGo