SBOS710D October   2014  – February 2018 LMH5401


  1. Features
  2. Applications
    1.     Distortion versus Frequency (G = 12 dB, SE-DE, RL = 200 Ω, VPP = 2 V)
  3. Description
    1.     LMH5401 Driving an ADC12J4000
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = 5 V
    6. 6.6 Electrical Characteristics: VS = 3.3 V
    7. 6.7 Typical Characteristics: 5 V
    8. 6.8 Typical Characteristics: 3.3 V
    9. 6.9 Typical Characteristics: 3.3-V to 5-V Supply Range
  7. Parameter Measurement Information
    1. 7.1  Output Reference Points
    2. 7.2  ATE Testing and DC Measurements
    3. 7.3  Frequency Response
    4. 7.4  S-Parameters
    5. 7.5  Frequency Response with Capacitive Load
    6. 7.6  Distortion
    7. 7.7  Noise Figure
    8. 7.8  Pulse Response, Slew Rate, and Overdrive Recovery
    9. 7.9  Power Down
    10. 7.10 VCM Frequency Response
    11. 7.11 Test Schematics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fully-Differential Amplifier
        1. Power Down and Ground Pins
      2. 8.3.2 Operations for Single-Ended to Differential Signals
        1. AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. DC-Coupled Input Signal Path Considerations for SE-DE Conversions
        3. Resistor Design Equations for Single-to-Differential Applications
        4. Input Impedance Calculations
      3. 8.3.3 Differential-to-Differential Signals
        1. AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. DC-Coupled, Differential-Input to Differential-Output Design Issues
      4. 8.3.4 Output Common-Mode Voltage
      5. 8.3.5 LMH5401 Comparison
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With a Split Supply
      2. 8.4.2 Operation With a Single Supply
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Stability
      2. 9.1.2 Input and Output Headroom Considerations
      3. 9.1.3 Noise Analysis
      4. 9.1.4 Noise Figure
      5. 9.1.5 Thermal Considerations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Driving Matched Loads
        2. Driving Unmatched Loads For Lower Loss
        3. Driving Capacitive Loads
        4. Driving ADCs
          1. SNR Considerations
          2. SFDR Considerations
          3. ADC Input Common-Mode Voltage Considerations : AC-Coupled Input
          4. ADC Input Common-Mode Voltage Considerations : DC-Coupled Input
        5. GSPS ADC Driver
        6. Common-Mode Voltage Correction
        7. Active Balun
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Do:
      2. 9.3.2 Don't:
  10. 10Power Supply Recommendations
    1. 10.1 Supply Voltage
    2. 10.2 Single-Supply
    3. 10.3 Split-Supply
    4. 10.4 Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

SFDR Considerations

The SFDR of the amplifier is usually set by the second-order or third-order harmonic distortion for single-tone inputs, and by the second-order or third-order intermodulation distortion for two-tone inputs. Harmonics and second-order intermodulation distortion can be filtered to some degree, but third-order intermodulation spurs cannot be filtered. The ADC generates the same distortion products as the amplifier, but as a result of the sampling and clock feedthrough, additional spurs (not linearly related to the input signal) are included.

When the spurs from the amplifier and filter are known, each individual spur can be directly added to the same spur from the ADC, as shown in Equation 14, to estimate the combined spur (spur amplitudes in dBc):

Equation 14. LMH5401 q_hdx_bos710.gif

This calculation assumes the spurs are in phase, but usually provides a good estimate of the final combined distortion.

For example, if the spur of the amplifier and filter equals the spur of the ADC, then the combined spur is 6 dB higher. To minimize the amplifier contribution (< 1 dB) to the overall system distortion, the spur from the amplifier and filter must be approximately 19 dB lower in amplitude than that of the converter. The combined spur calculated in this manner is usually accurate to within ±6 dB of the actual implementation; however, higher variations can be detected as a result of phase shift in the filter, especially in second-order harmonic performance.

This worst-case spur calculation assumes that the amplifier and filter spur of interest is in phase with the corresponding spur in the ADC, such that the two spur amplitudes can be added linearly. There are two phase-shift mechanisms that cause the measured distortion performance of the amplifier-ADC chain to deviate from the expected performance calculated using Equation 14: common-mode phase shift and differential phase shift.

Common-mode phase shift is the phase shift detected equally in both branches of the differential signal path including the filter. Common-mode phase shift nullifies the basic assumption that the amplifier, filter, and ADC spur sources are in phase. This phase shift can lead to better performance than predicted when the spurs become phase shifted, and there is the potential for cancellation when the phase shift reaches 180°. However, a significant challenge exists in designing an amplifier-ADC interface circuit to take advantage of a common-mode phase shift for cancellation: the phase characteristic of the ADC spur sources are unknown, thus the necessary phase shift in the filter and signal path for cancellation is also unknown.

Differential phase shift is the difference in the phase response between the two branches of the differential filter signal path. Differential phase shift in the filter as a result of mismatched components caused by nominal tolerance can severely degrade the even-order distortion of the amplifier-ADC chain. This effect has the same result as mismatched path lengths for the two differential traces, and causes more phase shift in one path than the other. Ideally, the phase response over frequency through the two sides of a differential signal path are identical, such that even-order harmonics remain optimally out of phase and cancel when the signal is taken differentially. However, if one side has more phase shift than the other, then the even-order harmonic cancellation is not as effective.

Single-order RC filters cause very little differential phase shift with nominal tolerances of 5% or less, but higher-order LC filters are very sensitive to component mismatch. For instance, a third-order Butterworth band-pass filter with a 100-MHz center frequency and a 20-MHz bandwidth creates as much as 20° of differential phase imbalance in a SPICE Monte Carlo analysis with 2% component tolerances. Therefore, although a prototype may work, production variance is unacceptable. In ac-coupled applications that require second- and higher-order filters between the LMH5401 and the ADC, a transformer or balun is recommended at the ADC input to restore the phase balance. For DC-coupled applications where a transformer or balun at the ADC input cannot be used, using first- or second-order filters is recommended to minimize the effect of differential phase shift because of the component tolerance.