SNCS103E November   2004  – August 2018 LMH6574

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Frequency Response vs VOUT
      2.      Frequency Response vs Gain
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Truth Table
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics ±5 V
    6. 6.6 Electrical Characteristics ±3.3 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Video Performance
      2. 7.2.2 Feedback Resistor Selection
      3. 7.2.3 Other Applications
      4. 7.2.4 Driving Capacitive Loads
      5. 7.2.5 ESD Protection
    3. 7.3 Device Functional Modes
      1. 7.3.1 SD vs EN
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multiplexer Expansion
  9. 9 Power Supply Recommendations
    1. 9.1 Power Dissipation
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

Whenever questions about layout arise, use the evaluation board LMH730276 as a guide. To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins. For long signal paths controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller ceramic capacitors should be placed as close to the device as possible. In the Functional Block Diagram, the capacitor between V+ and V− is optional, but is recommended for best second harmonic distortion. Another way to enhance performance is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply bypass.