SNAS668D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
Figure 41 illustrates the relationships between device states, the configuration pins, device initialization and configuration, and device operational modes. In hard pin configuration mode, the state of the configuration pins determines the configuration of the device as selected from all device states programmed in the on-chip ROM. In soft pin configuration mode, the state of the configuration pins determines the initialized state of the device as programmed in the on-chip EEPROM. In either mode, the host can update any device configuration after the device enables the host interface and the host writes a sequence that updates the device registers. Once the device configuration is set, the host can also write to the on-chip EEPROM for a new set of power-up defaults based on the configuration pin settings in the soft pin configuration mode. A system may transition a device from hard pin mode to soft pin mode by changing the state of the HW_SW_CTRL pin and then triggering a device power cycling through the PDN pin. In reset mode, the device disables the outputs so that unwanted sporadic activity associated with device initialization does not appear on the device outputs. Table 2 lists the functionality of the GPIO[5:0] pins during hard pin and soft pin modes.
PIN NAME | HARD PIN MODE | SOFT PIN MODE | ||
---|---|---|---|---|
FUNCTION | STATE | FUNCTION | STATE | |
GPIO0 | ROM page select for hard pin mode | 2 | Output synchronization (active low) | 2 |
GPIO1 | 2 | I2C slave address LSB select | 3 | |
GPIO2 | 2 | EEPROM page select for soft pin mode or register default mode | 3 | |
GPIO3 | 2 | 3 | ||
GPIO4 | 2 | Frequency margining enable | 2 | |
GPIO5 | 2 | Frequency margining offset select | 8 |