SWCS133D September 2015 – May 2019 TPS65094
PRODUCTION DATA.
As VSYS crosses above VSYS_UVLO_5V + VSYS_UVLO+5V_HYS, the cold-boot sequence is initiated by pulling the PMICEN pin high followed by driving the remaining control pins high in order. SLP_S3B and SLP_S4B may go high at the same time. SLP_S0B is not defined until the first transition to S0 after RSMRSTB deassertion. SLP_S0B is defined for all Sx power-state transitions after the first transition to S0.
Table 6-10 lists definitions of the timing delays. These timing delays also apply to the subsequent sequences. T0 to T10 are factory programmable to 0 ms, 2 ms, 4 ms, 8 ms, 16 ms, 24 ms, 32 ms, or
64 ms.