SWCS133D September   2015  – May 2019 TPS65094

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Options
    1. 3.1 OTP Comparison
  4. 4 Pin Configuration and Functions
    1.     RSK Package 64-Pin VQFN With Thermal Pad Top View
    2.     Pin Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Total Current Consumption
    6. 5.6  Electrical Characteristics: Reference and Monitoring System
    7. 5.7  Electrical Characteristics: Buck Controllers
    8. 5.8  Electrical Characteristics: Synchronous Buck Converters
    9. 5.9  Electrical Characteristics: LDOs
    10. 5.10 Electrical Characteristics: Load Switches
    11. 5.11 Digital Signals: I2C Interface
    12. 5.12 Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B, SLP_S0B)
    13. 5.13 Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
    14. 5.14 Timing Requirements
    15. 5.15 Switching Characteristics
    16. 5.16 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Good (PGOOD)
      2. 6.3.2 Register Reset Conditions
      3. 6.3.3 SMPS Voltage Regulators
        1. 6.3.3.1 Controller Overview
        2. 6.3.3.2 Converter Overview
        3. 6.3.3.3 DVS
        4. 6.3.3.4 Current Limit
      4. 6.3.4 LDOs and Load Switches
        1. 6.3.4.1 VTT LDO
        2. 6.3.4.2 LDOA1–LDOA3
        3. 6.3.4.3 Load Switches
      5. 6.3.5 Power Sequencing and VR Control
        1. 6.3.5.1 Cold Boot
        2. 6.3.5.2 Cold OFF
        3. 6.3.5.3 Connected Standby Entry and Exit
        4. 6.3.5.4 S0 to S3 Entry and Exit
        5. 6.3.5.5 S0 to S4/5 Entry and Exit
        6. 6.3.5.6 Emergency Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Off Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Active Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
        1. 6.5.1.1 F/S-Mode Protocol
    6. 6.6 Register Maps
      1. 6.6.1  VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
        1. Table 6-12 VENDORID Register Field Descriptions
      2. 6.6.2  DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
        1. Table 6-13 DEVICEID Register Field Descriptions
      3. 6.6.3  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
        1. Table 6-14 IRQ Register Field Descriptions
      4. 6.6.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
        1. Table 6-15 IRQ_MASK Register Field Descriptions
      5. 6.6.5  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
        1. Table 6-16 PMICSTAT Register Field Descriptions
      6. 6.6.6  OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
        1. Table 6-17 OFFONSRC Register Field Descriptions
      7. 6.6.7  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
        1. Table 6-18 BUCK1CTRL Register Field Descriptions
      8. 6.6.8  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
        1. Table 6-19 BUCK2CTRL Register Field Descriptions
      9. 6.6.9  BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
        1. Table 6-20 BUCK3CTRL Register Field Descriptions
      10. 6.6.10 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP Dependent]
        1. Table 6-21 BUCK4CTRL Register Field Descriptions
      11. 6.6.11 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP Dependent]
        1. Table 6-22 BUCK5CTRL Register Field Descriptions
      12. 6.6.12 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
        1. Table 6-23 BUCK6CTRL Register Field Descriptions
      13. 6.6.13 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
        1. Table 6-24 DISCHCNT1 Register Field Descriptions
      14. 6.6.14 DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
        1. Table 6-25 DISCHCNT2 Register Field Descriptions
      15. 6.6.15 DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
        1. Table 6-26 DISCHCNT3 Register Field Descriptions
      16. 6.6.16 POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
        1. Table 6-27 POK_DELAY Register Field Descriptions
      17. 6.6.17 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
        1. Table 6-28 FORCESHUTDN Register Field Descriptions
      18. 6.6.18 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
        1. Table 6-29 BUCK4VID Register Field Descriptions
      19. 6.6.19 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
        1. Table 6-30 BUCK5VID Register Field Descriptions
      20. 6.6.20 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
        1. Table 6-31 BUCK6VID Register Field Descriptions
      21. 6.6.21 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
        1. Table 6-32 LDOA2VID Register Field Descriptions
      22. 6.6.22 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
        1. Table 6-33 LDOA3VID Register Field Descriptions
      23. 6.6.23 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP Dependent]
        1. Table 6-34 VR_CTRL1 Register Field Descriptions
      24. 6.6.24 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
        1. Table 6-35 VR_CTRL2 Register Field Descriptions
      25. 6.6.25 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = OTP Dependent]
        1. Table 6-36 VR_CTRL3 Register Field Descriptions
      26. 6.6.26 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
        1. Table 6-37 GPO_CTRL Register Field Descriptions
      27. 6.6.27 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
        1. Table 6-38 PWR_FAULT_MASK1 Register Field Descriptions
      28. 6.6.28 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
        1. Table 6-39 PWR_FAULT_MASK2 Register Field Descriptions
      29. 6.6.29 DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
        1. Table 6-40 DISCHNT4 Register Field Descriptions
      30. 6.6.30 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
        1. Table 6-41 LDOA1CTRL Register Field Descriptions
      31. 6.6.31 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
        1. Table 6-42 PG_STATUS1 Register Field Descriptions
      32. 6.6.32 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
        1. Table 6-43 PG_STATUS2 Register Field Descriptions
        2. 6.6.32.1   PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
          1. Table 6-44 PWR_FAULT_STATUS1 Register Field Descriptions
        3. 6.6.32.2   PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
          1. Table 6-45 PWR_FAULT_STATUS2 Register Field Descriptions
      33. 6.6.33 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
        1. Table 6-46 TEMPHOT Register Field Descriptions
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Controller Design Procedure
          1. 7.2.2.1.1 Selecting the Output Capacitors
          2. 7.2.2.1.2 Selecting the Inductor
          3. 7.2.2.1.3 Selecting the FETs
          4. 7.2.2.1.4 Bootstrap Capacitor
          5. 7.2.2.1.5 Selecting the Input Capacitors
            1. 7.2.2.1.5.1 Setting the Current Limit
        2. 7.2.2.2 Converter Design Procedure
          1. 7.2.2.2.1 Selecting the Inductor
          2. 7.2.2.2.2 Selecting the Output Capacitors
          3. 7.2.2.2.3 Selecting the Input Capacitors
        3. 7.2.2.3 LDO Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Specific Application for TPS650944
    4. 7.4 Do's and Don'ts
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Revision History

Changes from C Revision (May 2019) to D Revision

  • Added "TPS650947" column to Summary of TPS65094x OTP Differences tableGo
  • Changed TPS650945 DEVICEID register to "Dh" and TPS650944 DEVICEID register to "Ch" in Summary of TPS65094x OTP Differences tableGo
  • Added TPS650947 settings to Section 6.6Go

Changes from B Revision (February 2017) to C Revision

  • Changed TPS65094x to TPS65094 in titleGo
  • Deleted variants from top of each pageGo
  • Added "BUCK3-5 Mode" row and "TPS650945" column to Summary of TPS65094x OTP Differences tableGo
  • Changed the description of the VTTFB pin in the Pin Functions tableGo
  • Changed VSYS to PVIN in the efficiency graphs for BUCK3, BUCK4, and BUCK5 in the Typical Characteristics sectionGo
  • Added to the description of the deassertion condition that causes an emergency shutdown in the Emergency Shutdown sectionGo
  • Added TPS650945 settings to Section 6.6Go
  • Changed OCP event to power fault event in the OCP bit description in the OFFONSRC Register Field Descriptions tableGo
  • Changed second reference of TPS650940 to TPS650944 for the bit reset values in the LDOA2VID Register Field Descriptions and LDOA3VID Register Field Descriptions tablesGo
  • Changed the bit values of the LDOA3_SLPVID[0] and LDOA3_VID[0] bits in the LDOA3VID Register figureGo

Changes from A Revision (June 2016) to B Revision

  • Changed functional block diagram to include TPS65094x family Go
  • Updated the PROCHOT pin description in the Pin Functions tableGo
  • Changed the values for LX3, LX4, LX5 from –1 V and 7 V to –2 V and 8 V in the Absolute Maximum Ratings tableGo
  • Changed the reset value of the LDOA2 VID register (LDOA2VID) to OTP dependentGo
  • Added the Receiving Notification of Documentation Updates sectionGo
  • Changed the Electrostatic Discharge Caution statementGo

Changes from September 11, 2015 to June 2, 2016 (from * Revision (September 2015) to A Revision)

  • Released full data sheet as SWCS133A version from SWCS130B versionGo
  • Changed device status to PROD_DATAGo
  • Changed VIN recommended minimum Go
  • Changed Features to improve description of converters Go
  • Changed Features to up to 400 mA of output current for load switchesGo
  • Changed functional block diagram to include TPS65094x family Go
  • Changed the Functional Block Diagram to include an inverter on PROCHOT pinGo
  • Changed PROCHOTB to PROCHOT throughout the documentGo
  • Changed minimum absolute-maximum-rating value for SW1, SW2, and SW6 in Section 5.1Go
  • Changed VSYS in Section 5.3, Recommended Operating ConditionsGo
  • Deleted nominal value from PVINVTT in Section 5.3, Recommended Operating ConditionsGo
  • Deleted (nu = symbol for efficiency) Go
  • Changed BUCK1 DC output voltage step size to show full range and be consistent in Section 5.7Go
  • Changed typo to match correct default of 1 V for ΔVOUT_TR in Section 5.7Go
  • Changed BUCK2 DC output voltage to show full range and be consistent in Section 5.7Go
  • Changed set condition for BUCK6 for VOUT range in Section 5.7 to match BUCK1 and BUCK2 Go
  • Updated formatting and added new OTP information for BUCK6 in Section 5.7Go
  • Updated formatting for BUCK3 DC output voltage in Section 5.8Go
  • Changed DC output voltage formatting for BUCK4 in Section 5.8Go
  • Changed maximum IOUT value for BUCK4 in Section 5.8 to match device capabilities Go
  • Changed IOUT and ΔVOUT/ΔIOUT for VTT LDO in Section 5.9 for new OTPs Go
  • Changed test conditions for VTT LDO overcurrent protection in Section 5.9Go
  • Changed Section 5.10 to show SWB1_2 RDSON is specified per output Go
  • Changed fSW values in Section 5.15 to provide more values Go
  • Changed current to 1.9 A to match SoC requirements in Table 6-1Go
  • Changed BUCK6, LDOA2, LDOA3 typical output voltage range to: OTP Dependent in Table 6-1Go
  • Changed table note to include additional DDR types in Table 6-1Go
  • Changed PMIC Functional Block Diagram to match specifications table Go
  • Changed PROCHOTB to PROCHOT in the Apollo Lake Power MapGo
  • Changed current ratings in Apollo Lake Power MapGo
  • Deleted SWBx PG from PG of PCH_PWROK in Table 6-2Go
  • Changed BUCK1–2 to all BUCKs and LDOAs in Section 6.3.3.3Go
  • Added Table 6-5 and Table 6-6 to Section 6.3.4.2Go
  • Added more DDR values to the table note in Table 6-7Go
  • Changed Section 6.3.5 to include LDOA1 and reset informationGo
  • Changed Section 6.6 to include multiple DDRsGo
  • Changed Figure 6-7 and Figure 6-8 to include alternate SWB1_2 TimingGo
  • Changed SWB1_2 from: V3P3A to: V1P8U in Table 6-10Go
  • Changed VDDQ voltage to OTP Dependent and SWBx to SWB1_2 in Table 6-11Go
  • Updated Figure 6-10 to include alternate SWB1_2 TimingGo
  • Changed Section 6.3.5.5 to include alternate SWB1_2 TimingGo
  • Changed Section 6.3.5.6 to include THERMTRIPB Go
  • Added the TPS65094x family OTP values to Section 6.6Go
  • Replaced VID values with link to full VID table in Table 6-18 and Table 6-19Go
  • Updated naming of bits in the TEMPHOT registerGo