SLVSCJ5B December   2015  – June 2020 TPS7H3301-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Standard DDR Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VTT/VO Sink and Source Regulator
      2. 7.3.2 Reference Input (VDDQSNS)
      3. 7.3.3 Reference Output (VTTREF)
      4. 7.3.4 EN Control (EN)
      5. 7.3.5 Power-Good Function (PGOOD)
      6. 7.3.6 VTT Current Protection
      7. 7.3.7 VIN UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD/VIN Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 VTT Output Capacitor
        4. 8.2.2.4 VTTSNS Connection
        5. 8.2.2.5 Low VIN Applications
        6. 8.2.2.6 S3 and Pseudo-S5 Support
        7. 8.2.2.7 Tracking Startup and Shutdown
        8. 8.2.2.8 Output Tolerance Consideration for VTT DIMM or Module Applications
        9. 8.2.2.9 LDO Design Guidelines
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over full temperature range, TJ = –55°C to 125°C, VDD/VIN = 3.3 V and 2.375 V, VLDOIN = 1.8 V, VDDQSNS = 1.8 V,
VTTSNS = 0.9 V, EN = VDD/VIN, Standard DDR Application unless otherwise noted
All voltage values are with respect to the network ground (AGND) pin unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVDD/Vin Supply current EN = 3.3 V, no load 18 30 mA
IVDD(SDN) Shutdown current EN = 0 V, VDDQSNS = 0, no load 3 5 mA
EN = 0 V, VDDQSNS > 0.78 V, no load 6.5 8
IVLDOIN Supply current of VLDOIN EN = 3.3 V, no load 575 1200 μA
IVLDOIN(SDN) Shutdown current of VLDOIN EN = 0 V, no load 50 100 μA
INPUT CURRENT
IVDDQSNS Input current, VDDQSNS EN = 3.3 V 4 6 μA
VTT/VO OUTPUT
VTTSNS Output DC voltage, VTT/VO VLDOIN = 2.5 V, VTTREF = 1.25 V (DDR1), IVTT/VO = 0 A 1.244 1.25 1.256 V
VLDOIN = 1.8 V, VTTREF = 0.9 V (DDR2), IVTT/VO = 0 A 0.894 0.9 0.906
VLDOIN = 1.5 V, VTTREF = 0.75 V (DDR3), IVTT/VO = 0 A 0.744 0.75 0.756
VLDOIN = 1.35 V, VTTREF = 0.675 V (DDR3L), IVTT/VO = 0 A 0.669 0.675 0.681
VLDOIN = 1.2 V, VTTREF = 0.6 V (DDR4), IVTT/VO = 0 A 0.594 0.6 0.606
VLDOIN – VTT/VO(3) VLDOIN > VTT/VO VDD/VIN = 2.95 V, VDDQSNS = 2.5 V, VTT/VO = VTTREF – 50 mV (DDR1), IO = 0.5 A 50 230 mV
VDD/VIN = 2.95 V, VDDQSNS = 2.5 V, VTT/VO = VTTREF – 50 mV (DDR1), IO = 1 A 101 300
VDD/VIN = 2.95 V, VDDQSNS = 2.5 V, VTT/VO = VTTREF – 50 mV (DDR1), IO = 2 A(2) 209 400
VDD/VIN = 2.375 V, VDDQSNS = 1.8 V, VTT/VO = VTTREF – 50 mV (DDR2), IO = 0.5 A(2) 54 230
VDD/VIN = 2.375 V, VDDQSNS = 1.8 V, VTT/VO = VTTREF – 50 mV (DDR2), IO = 1 A(2) 108 300
VDD/VIN = 2.375 V, VDDQSNS = 1.8 V, VTT/VO = VTTREF – 50 mV (DDR2), IO = 2 A(2) 228 400
VDD/VIN = 2.375 V, VDDQSNS = 1.5 V, VTT/VO = VTTREF – 50 mV (DDR3), IO = 0.5 A 52 230
VDD/VIN = 2.375 V, VDDQSNS = 1.5 V, VTT/VO = VTTREF – 50 mV (DDR3), IO = 1 A 104 300
VDD/VIN = 2.375 V, VDDQSNS = 1.5 V, VTT/VO = VTTREF – 50 mV (DDR3), IO = 2 A(2) 216 400
VDD/VIN = 2.375 V, VDDQSNS = 1.35 V, VTT/VO = VTTREF – 50 mV (DDR3L), IO = 0.5 A 50 230
VDD/VIN = 2.375 V, VDDQSNS = 1.35 V, VTT/VO = VTTREF – 50 mV (DDR3L), IO = 1 A 102 300
VDD/VIN = 2.375 V, VDDQSNS = 1.35 V, VTT/VO = VTTREF – 50 mV (DDR3L), IO = 2 A(2) 212 400
VDD/VIN = 2.375 V, VDDQSNS = 1.2 V, VTT/VO = VTTREF – 50 mV (DDR4), IO = 0.5 A 50 230
VDD/VIN = 2.375 V, VDDQSNS = 1.2 V, VTT/VO = VTTREF – 50 mV (DDR4), IO = 1 A 102 300
VDD/VIN = 2.375 V, VDDQSNS = 1.2 V, VTT/VO = VTTREF – 50 mV (DDR4), IO = 2 A(2) 210 400
VTT/VO(TOL) Output voltage tolerance to VTTREF IVTT/VO = –3 A, across VDD/VIN voltage range(2) 12 25 34 mV
IVTT/VO = 3 A, across VDD/VIN voltage range(2) –34 –25 –12
IVOSRCL VTT/VO source current limit With reference to VTTREF, VTTSNS = 90% × VTTREF 3.25 8 A
IVOSNCL VTT/VO/VTT sink current limit With reference to VTTREF, VTTSNS = 110% × VTTREF 3.5 5.5 A
RDSCHRG Discharge impedance VDDQSNS = 0 V, VTT/VO = 0.3 V, EN = 0 V, TA = 25°C 18 25 Ω
POWER-GOOD COMPARATOR
VTH(PG) VTT/VO PGOOD threshold PGOOD window lower threshold with respect to VVTTREF –23.5% –20% –17.5%
PGOOD window upper threshold with respect to VVTTREF 17.5% 20% 23.5%
PGOOD hysteresis 5%
TPGSTUPDLY PGOOD startup delay Startup rising edge, VTTSNS within 15% of VVTTREF 2 ms
VPGOODLOW Output low voltage ISINK = 4 mA 0.4 V
TPBADDLY PGOOD bad delay VTTSNS is outside of the ±20% PGOOD window 1 μs
IPGOODLK Leakage current VTTSNS = VTTREF (PGOOD high impedance),
PGOOD = VDD/VIN + 0.2 V		 1 μA
VDDQSNS AND VTTREF OUTPUT
VDDQSNS VDDQSNS voltage range 1 2.8 V
VVDDQSNS_UVLO VDDQSNS undervoltage lockout VDDQSNS rising 780 mV
VVDDQSNSUVHYS VDDQSNS undervoltage lockout hysteresis 20 mV
VVTTREF VTTREF voltage VDDQSNS / 2 V
VVTTREF VTTREF voltage tolerance to VDDQSNS –10 mA < IVTTREF < 10 mA, VDDQSNS = 2.5 V –15 15 mV
–10 mA < IVTTREF < 10 mA, VDDQSNS = 1.8 V –15 15
–10 mA < IVTTREF < 10 mA, VDDQSNS = 1.5 V –15 15
–10 mA < IVTTREF < 10 mA, VDDQSNS = 1.35 V –15 15
–10 mA < IVTTREF < 10 mA, VDDQSNS = 1.2 V –15 15
IVTTREFSRCL VVTTREF source current limit VTTREF = 0 V 10 40 mA
IVTTREFSNCCL VVTTREF sink current limit VTTREF = 0 V 6 40 mA
IVTTREFDIS VTTREF discharge current EN = 0 V, VDDQSNS = 0 V, VTTREF = 0.5 V 1.3 mA
UVLO/EN LOGIC THRESHOLD
VVINUVVIN UVLO threshold Wakeup, TA = 25°C 2.18 2.25 V
VVINUVVINHYS UVLO threshold hyteresis Hysteresis 50 mV
VENIH High-level input voltage Enable 1.7 V
VENIL Low-level input voltage Enable 0.3 V
VENYST Hysteresis voltage Enable 0.5 V
IENLEAK Logic input leakage current EN, TA = 25°C –1 1 μA
THERMAL SHUTDOWN
TSON Thermal shutdown threshold(1) Shutdown temperature 210 °C
Hysteresis 12
(1) Ensured by design, not production tested.
(2) Specified by characterization and not production tested.
(3) Dropout and headroom information provided to help designer in optimizing system efficiency.