SLUSCU6C August   2017  – January 2020 UCC256301

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hybrid Hysteretic Control
      2. 7.3.2  Regulated 12-V Supply
      3. 7.3.3  Feedback Chain
      4. 7.3.4  Optocoupler Feedback Signal Input and Bias
      5. 7.3.5  System External Shut Down
      6. 7.3.6  Pick Lower Block and Soft Start Multiplexer
      7. 7.3.7  Pick Higher Block and Burst Mode Multiplexer
      8. 7.3.8  VCR Comparators
      9. 7.3.9  Resonant Capacitor Voltage Sensing
      10. 7.3.10 Resonant Current Sensing
      11. 7.3.11 Bulk Voltage Sensing
      12. 7.3.12 Output Voltage Sensing
      13. 7.3.13 High Voltage Gate Driver
      14. 7.3.14 Protections
        1. 7.3.14.1 ZCS Region Prevention
        2. 7.3.14.2 Over Current Protection (OCP)
        3. 7.3.14.3 Over Output Voltage Protection (VOUTOVP)
        4. 7.3.14.4 Over Input Voltage Protection (VINOVP)
        5. 7.3.14.5 Under Input Voltage Protection (VINUVP)
        6. 7.3.14.6 Boot UVLO
        7. 7.3.14.7 RVCC UVLO
        8. 7.3.14.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Burst Mode Control
      2. 7.4.2 High Voltage Start-Up
      3. 7.4.3 X-Capacitor Discharge
      4. 7.4.4 Soft-Start and Burst-Mode Threshold
      5. 7.4.5 System States and Faults State Machine
      6. 7.4.6 Waveform Generator State Machine
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 BW Pin Voltage Divider
        18. 8.2.2.18 ISNS Pin Differentiator
        19. 8.2.2.19 VCR Pin Capacitor Divider
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Soft-Start Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Pin Capacitor
    2. 9.2 Boot Capacitor
    3. 9.3 RVCC Pin Capacitor
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support (if applicable)
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

All voltages are with respect to GND, –40°C < TJ = TA < 125°C, VCC = 15 V, currents are positive into and negative out of the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VCCShort Below this threshold, use reduced start up current 0.5 0.6 0.7 V
VCCReStartJfet Below this threshold, re-enable JFET. 10.2 10.5 10.8 V
VCCStartSelf In self bias mode, gate starts switching above this level 25 26 28 V
VCCLatch VCC regulation voltage during latched state 13.5 14.3 15.0 V
SUPPLY CURRENT
ICCSleep Current drawn from VCC rail during burst off period VCC = 15 V 475 565 700 µA
ICCRun Current drawn from VCC Pin while gate is switching. Excluding Gate Current VCC = 15 V, maximum dead time 1.75 2.2 2.65 mA
ICCLatch Current drawn from VCC pin in latched state VCC = 15 V 150 330 777 µA
REGULATED SUPPLY
VRVCC Regulated supply voltage VCC = 15 V 11.60 12 12.40 V
VCC = 13 V 11.2 11.8 12.25 V
VRVCCUVLO RVCC under voltage lock out voltage (1) 7 V
HIGH VOLTAGE STARTUP
IHVLow Reduced startup pin current 0.28 0.41 0.54 mA
IHVHigh Full startup pin current 7.6 10.20 12.6 mA
IHVLeak HV current source leakage current 1.40 3.37 7.55 µA
IHVZCD Highest AC zero crossing detection test current 0.63 0.77 0.89 mA
IXCAPDischarge X-cap discharge current 9.6 11.47 13.5 mA
tXCAPZCD AC zero crossing detection window length for first three test current stage (1) 10 11.85 14 ms
tXCAPZCDLast AC zero crossing detection window length for final test current stage (1) 43 46 52 ms
tXCAPIdle AC zero crossing detection idle period length (1) 635 704 772 ms
tXCAPDischarge Time for X-cap discharge current active (1) 327 358 390 ms
BULK VOLTAGE SENSE
VBLKStart Input voltage that allows LLC to start switching Voltage rising 2.969 3.05 3.095 V
VBLKStop Input voltage that forces LLC operation to stop Voltage falling 0.85 0.87 0.93 V
VBLKOVRise Input voltage that causes switching to stop Voltage rising 3.94 4.03 4.11 V
VBLKOVFall Input voltage that causes switching to re-start Voltage falling 3.64 3.76 3.86 V
FEEDBACK PIN
RFBInternal Internal pull down resistor value 90.7 101.5 112.3 kΩ
IFB FB internal current source 76.5 85.1 93.6 µA
f-3dB Feedback chain -3dB cut off frequency (2) 1 MHz
RESONANT CURRENT SENSE
VISNS_OCP1 OCP1 threshold 3.97 4.03 4.07 V
VISNS_OCP1_SS OCP1 threshold during soft start (1) 5 V
VISNS_OCP2 OCP2 threshold 0.68 0.84 0.99 V
VISNS_OCP3 OCP3 threshold 0.49 0.64 0.79 V
TISNS_OCP2 The time the average input current needs to stay above OCP2 threshold before OCP2 is triggered (1) 2 ms
TISNS_OCP3 The time the average input current needs to stay above OCP3 threshold before OCP3 is triggered (1) 50 ms
VIpolarityHyst Resonant current polarity detection hysteresis 16.9 30.7 44.7 mV
nOCP1 Number of OCP1 cycles before OCP1 fault is tripped (1) 4
RESONANT CAPACITOR VOLTAGE SENSE
VCM Internal common mode voltage 2.91 3.02 3.14 V
IRAMP Frequency compensation ramp current source value 1.63 1.84 2.10 mA
IMismatch Pull up and pull down ramp current source mismatch (3) –1.25 1.25 %
SOFT START
ISSUp Current output from SS pin to charge up the soft start capacitor 21.8 25.8 29.8 µA
RSSDown SS pin pull down resistance
ZCS or OCP1 222 401 580 Ω
GATE DRIVER
VLOL LO output low voltage Isink = 20 mA 0.027 0.052 0.087 V
VRVCC - VLOH LO output high voltage Isource = 20 mA 0.113 0.178 0.263 V
VHOL - VHS HO output low voltage Isink = 20 mA 0.027 0.053 0.087 V
VHB - VHOH HO output high voltage Isource = 20 mA 0.113 0.173 0.263 V
VHB-HSUVLORise High side gate driver UVLO rise threshold 7.35 7.94 8.70 V
VHB-HSUVLOFall High side gate driver UVLO fall threshold 6.65 7.25 7.76 V
Isource_pk HO, LO peak source current (2) –0.6 A
Isink_pk HO, LO peak sink current (2) 1.2 A
BOOTSTRAP
IBOOT_QUIESCENT (HB - HS) quiescent current HB – HS = 12 V 51.10 74.40 97.70 µA
IBOOT_LEAK HB to GND leakage current 0.02 0.40 5.40 µA
tChargeBoot Length of charge boot state 234 267 296 µs
BIAS WINDING
VBWOVRise Output voltage OVP –4.1 –3.97 –3.86 V
BURST MODE
RLL LL voltage scaling resistor value 240 250 258 kΩ
ADAPTIVE DEADTIME
dVHS/dt Detectable PSN slew rate (1) ±1 ±50 V/ns
FAULT RECOVERY
tPauseTimeOut Paused timer (1) 1 s
THERMAL SHUTDOWN
TJ_r Thermal shutdown temperature (1) Temperature rising 125 140 °C
(1) Not production tested. Ensured by characterization
(2) Not production tested. Ensured by design.
(3) IMismatch calculated as average of (IPD-(IPD+IPU)/((IPD+IPU)/2) and (IPU-(IPD+IPU)/((IPD+IPU)/2)