SLUSBW3D March   2014  – December 2017 UCC28630 , UCC28631 , UCC28632 , UCC28633 , UCC28634

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Application Measured Regulation
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     PIN Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information (UCC28630, UCC28631)
    5. 7.5 Thermal Information (UCC28632, UCC28633, (UCC28630, UCC28634)
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Voltage Current Source Start-Up Operation
      2. 8.3.2  AC Input UVLO / Brownout Protection
      3. 8.3.3  Active X-Capacitor Discharge (UCC28630 and UCC28633 only)
        1. 8.3.3.1 Improved Performance with UCC28630 and UCC28633
      4. 8.3.4  Magnetic Input and Output Voltage Sensing
      5. 8.3.5  Fixed-Point Magnetic Sense Sampling Error Sources
      6. 8.3.6  Magnetic Sense Resistor Network Calculations
        1. 8.3.6.1 Step 1
        2. 8.3.6.2 Step 2
        3. 8.3.6.3 Step 3
        4. 8.3.6.4 Step 4
      7. 8.3.7  Magnetic Sensing: Power Stage Design Constraints
      8. 8.3.8  Magnetic Sense Voltage Control Loop
      9. 8.3.9  Peak Current Mode Control
      10. 8.3.10 IPEAK Adjust vs. Line
      11. 8.3.11 Primary-Side Constant-Current Limit (CC Mode)
      12. 8.3.12 Primary-Side Overload Timer (UCC28630 only)
      13. 8.3.13 Overload Timer Adjustment (UCC28630 only)
      14. 8.3.14 CC-Mode IOUT(lim) Adjustment
      15. 8.3.15 Fault Protections
      16. 8.3.16 Pin-Fault Detection and Protection
      17. 8.3.17 Over-Temperature Protection
      18. 8.3.18 External Fault Input
      19. 8.3.19 External SD Pin Wake Input (except UCC28633)
      20. 8.3.20 External Wake Input at VSENSE Pin (UCC28633 Only)
      21. 8.3.21 Mode Control and Switching Frequency Modulation
      22. 8.3.22 Frequency Dither For EMI (except UCC28632)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Internal Key Parameters
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Notebook Adapter, 19.5 V, 65 W
      2. 9.2.2 UCC28630 Application Schematic
      3. 9.2.3 Design Requirements
      4. 9.2.4 Detailed Design Procedure
        1. 9.2.4.1  Custom Design With WEBENCH® Tools
        2. 9.2.4.2  Input Bulk Capacitance and Minimum Bulk Voltage
        3. 9.2.4.3  Transformer Turn Ratio
        4. 9.2.4.4  Transformer Magnetizing Inductance
        5. 9.2.4.5  Current Sense Resistor RCS
        6. 9.2.4.6  Transformer Constraint Verification
        7. 9.2.4.7  Transformer Selection and Design
        8. 9.2.4.8  Slope Compensation Verification
        9. 9.2.4.9  Power MOSFET and Output Rectifier Selection
        10. 9.2.4.10 Output Capacitor Selection
        11. 9.2.4.11 Calculation of CC Mode Limit Point
        12. 9.2.4.12 VDD Capacitor Selection
        13. 9.2.4.13 Magnetic Sense Resistor Network Selection
        14. 9.2.4.14 Output LED Pre-Load Resistor Calculation
      5. 9.2.5 External Wake Pulse Calculation at VSENSE Pin (UCC28633 Only)
      6. 9.2.6 Energy Star Average Efficiency and Standby Power
      7. 9.2.7 Application Performance Plots
    3. 9.3 Dos and Don'ts
      1. 9.3.1 Test and Debug Recommendations
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 HV Pin
      2. 11.1.2 VDD Pin
      3. 11.1.3 VSENSE Pin
      4. 11.1.4 CS Pin
      5. 11.1.5 SD Pin
      6. 11.1.6 DRV Pin
      7. 11.1.7 GND Pin
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Frequency Dither For EMI (except UCC28632)

To help ease EMI compliance of the system, the device dithers the switching frequency over time. This dithering of frequency is active only above the light-load region threshold (PLL(%)) point on the modulator curve. In the light load regions, frequency dither is disabled. The frequency dither follows a repeating pattern, in the sequence:

\{(fNOM), (fNOM + 6.7%), (fNOM + 6.7%), fNOM), (fNOM – 6.7%), (fNOM – 6.7%), (fNOM), . . . .\}

The controller dwells at each frequency for 1 ms. The pattern repeats every 6 ms, as shown graphically in Figure 43.

NOTE

The device always dithers frequency between 6.7% and –6.7% at every operating point in the modulator. The dither frequency delta is not an absolute delta, it scales with actual operating frequency, depending on the exact operating point value.

UCC28630 UCC28631 UCC28632 UCC28633 UCC28634 fig43_lusbw3.gifFigure 43. Frequency Dither Pattern Details

In order to balance the power flow and reduce and output ripple as a consequence of frequency dithering, the device automatically adjusts peak-current demand in inverse-proportion to the square-root of the frequency dither deviation. Thus, since the power flow (in DCM) is given by (½ × L × I2 × fSW), this balances the power flow, and cancels the output ripple as a consequence of frequency dithering.