SNLS346C August   2011  – June 2014 DS90UR903Q-Q1 , DS90UR904Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing for PCLK
    7. 6.7  Serial Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (See )
    8. 6.8  Serial Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
    9. 6.9  Serializer Switching Characteristics
    10. 6.10 Deserializer Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Typical Application Diagram
      2. 7.2.2 Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Signal Quality Enhancers
        1. 7.3.2.1 Des - Receiver Input Equalization (EQ)
      3. 7.3.3 Emi Reduction
        1. 7.3.3.1 Des - Receiver Staggered Output
        2. 7.3.3.2 Des Spread Spectrum Clocking
    4. 7.4 Device Functional Modes
      1. 7.4.1 LVCMOS VDDIO Option
      2. 7.4.2 Powerdown
      3. 7.4.3 Pixel Clock Edge Select (TRFB/RRFB)
    5. 7.5 Programming
      1. 7.5.1 Description of Serial Control Bus
      2. 7.5.2 ID[X] Address Decoder
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Typical Application Connection
        2. 8.2.2.2 AC Coupling
        3. 8.2.2.3 Power Up Requirements and PDB PIN
        4. 8.2.2.4 Transmission Media
        5. 8.2.2.5 Serial Interconnect Guidelines
        6. 8.2.2.6 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 10 MHz to 43 MHz Input PCLK Support
  • 210 Mbps to 903 Mbps Data Throughput
  • Single Differential Pair Interconnect
  • Embedded Clock with DC Balanced Coding to Support AC-coupled Interconnects
  • Capable to Drive up to 10 meters Shielded Twisted-Pair
  • I2C Compatible Serial Interface for Device Configuration
  • Single Hardware Device Addressing Pin
  • LOCK Output Reporting Pin to Validate Link Integrity
  • Integrated Termination Resistors
  • 1.8V- or 3.3V-compatible Parallel Bus Interface
  • Single Power Supply at 1.8V
  • ISO 10605 ESD and IEC 61000-4-2 ESD Compliant
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • Temperature Range −40°C to +105°C
  • No Reference Clock Required on Deserializer
  • Programmable Receive Equalization
  • EMI/EMC Mitigation
    • DES Programmable Spread Spectrum (SSCG) outputs
    • DES Receiver Staggered Outputs

2 Applications

  • Automotive Display Systems
    • Central Information Displays
    • Navigation Displays
    • Rear Seat Entertainment

3 Description

The DS90UR903Q/DS90UR904Q chipset offers a FPD-Link II interface with a high-speed forward channel for data transmission over a single differential pair. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE). The serializer converts 21 bit data over a single high-speed serial stream. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The Serializer is offered in a 40-pin WQFN package and the Deserializer is offered in a 48-pin WQFN package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UR903Q-Q1 WQFN RTA (40) 6.00 mm × 6.00 mm
DS90UR904Q-Q1 WQFN RHS (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.


Simplified Schematic

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Typical Eye Diagram

tc01_43MHz_eye_diag_snls346.gif