JAJSFF6B june 2018 – september 2020 DS90C189-Q1
PRODUCTION DATA
| PARAMETER | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| TSTC | IN_n Setup to IN_CLK | See Figure 7-6 | 0 | ns | ||
| THTC | IN_n Hold from IN_CLK | See Figure 7-6 | 2.5 | ns | ||
| LLHT | LVDS Low-to-High Transition Time See Figure 7-4 | 0.33 | ns | |||
| LHLT | LVDS High-to-Low Transition Time See Figure 7-4 | 0.33 | ns | |||
| TBIT | LVDS Output Bit Width | MODE0 = GND | 1/7 TCIP | ns | ||
| MODE0 = VDD | 2/7 TCIP | ns | ||||
| TPPOS0 | Transmitter Output Pulse Positions Normalized for Bit 0 | See Figure 7-9 | 1 | UI | ||
| TPPOS1 | Transmitter Output Pulse Positions Normalized for Bit 1 | See Figure 7-9 | 2 | UI | ||
| TPPOS2 | Transmitter Output Pulse Positions Normalized for Bit 2 | See Figure 7-9 | 3 | UI | ||
| TPPOS3 | Transmitter Output Pulse Positions Normalized for Bit 3 | See Figure 7-9 | 4 | UI | ||
| TPPOS4 | Transmitter Output Pulse Positions Normalized for Bit 4 | See Figure 7-9 | 5 | UI | ||
| TPPOS5 | Transmitter Output Pulse Positions Normalized for Bit 5 | See Figure 7-9 | 6 | UI | ||
| TPPOS6 | Transmitter Output Pulse Positions Normalized for Bit 6 | See Figure 7-9 | 7 | UI | ||
| Δ_TPPOS | Variation in Transmitter Pulse Position (Bit 6 — Bit 0) | See Figure 7-9 | ±0.06 | UI | ||
| TCCS | LVDS Channel to Channel Skew | 110 | ps | |||
| TJCC | Jitter Cycle-to-Cycle | MODE0 = GND, f = 105 MHz | 0.176 | UI | ||
| TPLLS | Phase Lock Loop Set (Enable Time) | See Figure 7-7 | 1 | ms | ||
| TPDD | Powerdown Delay | See Figure 7-8 | 100 | ns | ||
| TSD | Latency Delay | MODE0 = GND See Figure 7-11 | 2*TCIP + 10.54 | 2*TCIP + 19.38 | ns | |
| TLAT | Latency Delay for Single Pixel In / Dual Pixel Out Mode | MODE0 = VDD See Figure 7-10 | 9*TCIP + 4.19 | ns | ||