JAJSNC5 april   2023 LM5171-Q1

ADVANCE INFORMATION  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 7.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 7.3.3  High Voltage Inputs (HV1, HV2)
      4. 7.3.4  Current Sense Amplifier
      5. 7.3.5  Control Commands
        1. 7.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 7.3.5.2 Direction Command (DIR1 and DIR2)
        3. 7.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 7.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 7.3.6.1 Individual Channel Current Monitor
        2. 7.3.6.2 Multiphase Total Current Monitoring
      7. 7.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 7.3.8  Inner Current Loop Error Amplifier
      9. 7.3.9  Outer Voltage Loop Error Amplifier
      10. 7.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 7.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 7.3.10.2 DEM Programming
        3. 7.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 7.3.10.4 SS Pin as the Restart Timer
      11. 7.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 7.3.12 Emergent Latched Shutdown (DT/SD)
      13. 7.3.13 PWM Comparator
      14. 7.3.14 Oscillator (OSC)
      15. 7.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 7.3.16 Overvoltage Protection (OVP)
      17. 7.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 7.3.17.1 Multiphase in Star Configuration
        2. 7.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 7.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 7.3.18 Thermal Shutdown
    4. 7.4 Programming
      1. 7.4.1 Dynamic Dead Time Adjustment
      2. 7.4.2 UVLO Programming
    5. 7.5 I2C Serial Interface
      1. 7.5.1 REGFIELD Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 Typical Application
      1. 8.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Determining the Duty Cycle
          2. 8.2.1.2.2  Oscillator Programming
          3. 8.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.2.1.2.4  Current Sense (RCS)
          5. 8.2.1.2.5  Current Setting Limits (ISETx)
          6. 8.2.1.2.6  Peak Current Limit
          7. 8.2.1.2.7  Power MOSFETS
          8. 8.2.1.2.8  Bias Supply
          9. 8.2.1.2.9  Boot Strap
          10. 8.2.1.2.10 OVP
          11. 8.2.1.2.11 Dead Time
          12. 8.2.1.2.12 Channel Current Monitor (IMONx)
          13. 8.2.1.2.13 UVLO Pin Usage
          14. 8.2.1.2.14 HVx Pin Configuration
          15. 8.2.1.2.15 Loop Compensation
          16. 8.2.1.2.16 Soft Start
          17. 8.2.1.2.17 PWM to ISET Pins
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.1 REGFIELD Registers

REGFIELD Registers lists the memory-mapped registers for the REGFIELD registers. All register offset addresses not listed in REGFIELD Registers should be considered as reserved locations and the register contents should not be modified.

Table 7-4 REGFIELD Registers
AddressAcronymRegister NameSection
3hCLEAR_FAULTSCLEAR_FAULTSCLEAR_FAULTS Register (Address = 3h) [Reset = 00h]
78hFAULT_STATUSFAULT_STATUSFAULT_STATUS Register (Address = 78h) [Reset = 00h]
D0hDEVICE_STATUS_1DEVICE_STATUS_1DEVICE_STATUS_1 Register (Address = D0h) [Reset = 00h]
D1hDEVICE_STATUS_2DEVICE_STATUS_2DEVICE_STATUS_2 Register (Address = D1h) [Reset = 00h]

Complex bit access types are encoded to fit into small table cells. REGFIELD Access Type Codes shows the codes that are used for access types in this section.

Table 7-5 REGFIELD Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nCLEAR FAULTValue after reset or the default value

7.5.1.1 CLEAR_FAULTS Register (Address = 3h) [Reset = 00h]

CLEAR_FAULTS is shown in CLEAR_FAULTS Register Field Descriptions.

Return to the Summary Table.

Clear all latched status flags in 0x78 register

Table 7-6 CLEAR_FAULTS Register Field Descriptions
BitFieldTypeResetDescription
7-0CLEAR_FAULTSR/W0hAccessing the address is enough to clear fault

7.5.1.2 FAULT_STATUS Register (Address = 78h) [Reset = 00h]

FAULT_STATUS is shown in FAULT_STATUS Register Field Descriptions.

Return to the Summary Table.

Fault status

Table 7-7 FAULT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-6NILR0hThis bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations 0 is returned.
5BOOTUV1R0hBoot UV (HB-SW undervoltage) Channel 1

0h = no fault

1h = fault

4BOOTUV2R0hBoot UV (HB-SW undervoltage) Channel 2

0h = no fault

1h = fault

3ILIM1R0hPeak Current limit Channel 1

0h = no fault

1h = fault

2ILIM2R0hPeak Current limit Channel 2

0h = no fault

1h = fault

1OVPR0hOver voltage fault

0h = no fault

1h = fault

0TSDR0hThermal shutdown fault

0h = no fault

1h = fault

7.5.1.3 DEVICE_STATUS_1 Register (Address = D0h) [Reset = 00h]

DEVICE_STATUS_1 is shown in DEVICE_STATUS_1 Register Field Descriptions.

Return to the Summary Table.

Informational bits about the part status

Table 7-8 DEVICE_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
7EN1R0hChannel 1 enable status

0h = Channel 1 disabled

1h = Channel 1 enabled

6EN2R0hChannel 2 enable status

0h = Channel 2 disabled

1h = Channel 2 enabled

5DEM1R0hChannel 1 DEM status

0h = Channel 1 FPWM

1h = Channel 1 DEM

4DEM2R0hChannel 2 DEM status

0h = Channel 2 FPWM

1h = Channel 2 DEM

3DIR1R0hDIR 1 status

0h = DIR1 low

1h = DIR1 high

2DIR2R0hDIR 2 status

0h = DIR2 low

1h = DIR2 high

1DIR_INVALID1R0hInvalid DIR1 command

0h = Valid DIR1 command

1h = Invalid DIR1 command

0DIR_INVALID2R0hInvalid DIR2 command

0h = Valid DIR2 command

1h = Invalid DIR2 command

7.5.1.4 DEVICE_STATUS_2 Register (Address = D1h) [Reset = 00h]

DEVICE_STATUS_2 is shown in DEVICE_STATUS_2 Register Field Descriptions.

Return to the Summary Table.

Informational bits about the part status

Table 7-9 DEVICE_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
7-6SPARER0hSpare register - Preset LOW
5OPTR0hOPT pin status

0h = OPT low

1h = OPT high

4SS1_DONER0hSS channel 1 completion status

0h = SS1 not done

1h = SS1 done

3SS2_DONER0hSS channel 2 completion status

0h = SS2 not done

1h = SS2 done

2SDR0hSD/DT pin status

0h = Part not in SD

1h = Part in SD

1ADAPT_DTR0hAdaptive deadtime status

0h = No adaptive deadtime

1h = Adaptive deadtime

0VCC_UVR0hVCC UV status

0h = VCC not in UV

1h = VCC in UV