JAJSNC5 april   2023 LM5171-Q1

ADVANCE INFORMATION  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 7.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 7.3.3  High Voltage Inputs (HV1, HV2)
      4. 7.3.4  Current Sense Amplifier
      5. 7.3.5  Control Commands
        1. 7.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 7.3.5.2 Direction Command (DIR1 and DIR2)
        3. 7.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 7.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 7.3.6.1 Individual Channel Current Monitor
        2. 7.3.6.2 Multiphase Total Current Monitoring
      7. 7.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 7.3.8  Inner Current Loop Error Amplifier
      9. 7.3.9  Outer Voltage Loop Error Amplifier
      10. 7.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 7.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 7.3.10.2 DEM Programming
        3. 7.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 7.3.10.4 SS Pin as the Restart Timer
      11. 7.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 7.3.12 Emergent Latched Shutdown (DT/SD)
      13. 7.3.13 PWM Comparator
      14. 7.3.14 Oscillator (OSC)
      15. 7.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 7.3.16 Overvoltage Protection (OVP)
      17. 7.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 7.3.17.1 Multiphase in Star Configuration
        2. 7.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 7.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 7.3.18 Thermal Shutdown
    4. 7.4 Programming
      1. 7.4.1 Dynamic Dead Time Adjustment
      2. 7.4.2 UVLO Programming
    5. 7.5 I2C Serial Interface
      1. 7.5.1 REGFIELD Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 Typical Application
      1. 8.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Determining the Duty Cycle
          2. 8.2.1.2.2  Oscillator Programming
          3. 8.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.2.1.2.4  Current Sense (RCS)
          5. 8.2.1.2.5  Current Setting Limits (ISETx)
          6. 8.2.1.2.6  Peak Current Limit
          7. 8.2.1.2.7  Power MOSFETS
          8. 8.2.1.2.8  Bias Supply
          9. 8.2.1.2.9  Boot Strap
          10. 8.2.1.2.10 OVP
          11. 8.2.1.2.11 Dead Time
          12. 8.2.1.2.12 Channel Current Monitor (IMONx)
          13. 8.2.1.2.13 UVLO Pin Usage
          14. 8.2.1.2.14 HVx Pin Configuration
          15. 8.2.1.2.15 Loop Compensation
          16. 8.2.1.2.16 Soft Start
          17. 8.2.1.2.17 PWM to ISET Pins
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Voltage Loop Compensation

The typical bi-directional application with HV voltage regulation and LV voltage regulation is shown in Figure 8-5. Connect the error voltage of the outer voltage loop error amplifiers (ERRHV and ERRLV) to ISETx as the reference for the inner current loop.

It is advised that the outer voltage loop crossover frequency fCV should be one decade below that of the inner current loop crossover frequency fCI. And boost outer voltage loop crossover frequency should also be below 1/5 of the Right-Half-Plane Zero (RHPZ).

GUID-20230210-SS0I-3SMG-SSZ4-BHZ8ZW61JTZJ-low.svg Figure 8-5 Outer Voltage Loop Control

Type-II compensator as shown in Figure 8-5 is recommended to stabilize the voltage loop for both buck and boost mode operations.

Buck mode compensation will be analyzed as an example. The transfer function of the compensator of buck mode can be found as:

Equation 60. Gcvs=v^ISETv^LVAVM×ωZEAs×1+sωZEA1+sωHF×KISET

where

Equation 61. AVMRLCOMPRLFBT
Equation 62. ω Z E A = 1 R L C O M P × C L C O M P
Equation 63. ωHF1RLCOMP×CLHF
Equation 64. K I S E T = R I S E T B R I S E T T + R I S E T B

The total open-loop gain of the outer voltage loop of buck mode Tv_BK(s) is the product of Gvs_BK(s) and Gcv(s):

Equation 65. Tv_BKs=Gvs_BKs×Gcvs

Or:

Equation 66. Tv_BKs=Kdc_BK×1+sωZ_vl1+sωZ_il×AVM×ωZEAs×1+sωZEA1+sωHF×KISET

To tailor the total outer voltage loop gain to crossover at fCV, select the components of the compensation network according to the following guidelines, then fine tune the network for optimal loop performance.

  1. Choose a value for RLFBT based on the bias current and power dissipation,
  2. The zero fz is placed around 1/5 of target crossover frequency fCV,
  3. The pole fp2 is placed at approximately 10 times of fCV,
  4. The total open-loop gain is set to unity at fCI, namely,

Equation 67. Gvs_BK2i×π×fCV×Gcv2i×π×fCV=1

Therefore, the compensation components can be derived from the above equations as:

Equation 68. RLCOMP=RLFBTKdc_BK×1+2i×π×fCVωZ_vl1+2i×π×fCVωZ_il×KISETCLCOMP=12i×π×fCV5×RCOMPCLHF=12i×π×10×fCV×RCOMP

The compensator of boost voltage loop can be designed similarly. Please note that boost voltage loop crossover frequency should also be below 1/5 of the Right-Half-Plane Zero (RHPZ).