JAJSNC5 april 2023 LM5171-Q1
ADVANCE INFORMATION
Each channel of the LM5171-Q1 has a pulse width modulator (PWM) employing a high-speed comparator. It compares the internal ramp signal and the COMP pin signal to produce the PWM duty cycle. Note that the COMP signal passes through a 1-V DC offset before it is applied to the PWM comparator, as shown in Figure 7-12. Owing to this DC offset, the duty cycle can reduce to zero when the COMP pin or SS pin is pulled lower than 1 V. The maximum duty cycle is limited by the 100-ns typical minimum off-time, with the worst case max limit of 150 ns. Note that the programmed dead time may reduce the maximum duty cycle because it is additional to the minimum off-time. Therefore, the maximum duty cycle, for both buck and boost mode operation, is determined by Equation 15.
Where
This maximum duty cycle limits the minimum voltage step-down ratio in buck mode operation, and the maximum step-up ratio in boost mode operation.