JAJSAR0B March 2007 – October 2017 LM95214
PRODUCTION DATA.
Register Name | Command Byte
(Hex) |
Read/
Write |
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | POR Default (Hex) |
---|---|---|---|---|---|---|---|---|---|---|---|
Common Status Register | 0×02 | RO | BUSY | NR | – | – | SR4F | SR3F | SR2F | SR1F | 0×00 |
Bit(s) | Bit Name | Read/Write | Description |
---|---|---|---|
7 | BUSY | RO | Busy bit (device converting) |
6 | NR | RO | Not Ready bit (30 ms), indicates power up initialization sequence is in progress |
5–4 | – | RO | Reserved – will report 0 when read. |
3 | SR4F | RO | Status Register 4 Flag:
1 – indicates that Status Register 4 has at least one bit set 0 – indicates that all of Status Register 4 bits are cleared |
2 | SR3F | RO | Status Register 3 Flag:
1 – indicates that Status Register 3 has at least one bit set 0 – indicates that all of Status Register 3 bits are cleared |
1 | SR2F | RO | Status Register 2 Flag:
1 – indicates that Status Register 2 has at least one bit set 0 – indicates that all of Status Register 2 bits are cleared |
0 | SR1F | RO | Status Register 1 Flag:
1 – indicates that Status Register 1 has at least one bit set 0 – indicates that all of Status Register 1 bits are cleared |