JAJSEA1 December 2017 PGA302
PRODUCTION DATA.
The PGA302 has DVDD regulator that provides the 1.8-V regulated voltage for the digital circuitry.
The Power-On Reset signal to the digital core is deasserted when DVDD are in regulation. Figure 9 shows the block diagram representation of the digital power-on-reset (POR) signal generation and Figure 10 shows the digital POR signal assertion and deassertion timing during VDD ramp up and ramp down. This timing shows that during power up, the digital core and the processor remains in reset state until DVDD is at stable levels.