JAJSNP9 データシート

JAJSNP9 January 2024 TAA5412-Q1

ADVANCE INFORMATION

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RTV|32
- MPQF166B
RGE|24
- MPQF124G

サーマルパッド・メカニカル・データ

発注情報

jajsnp9_oa

7.2 TAA5412-Q1 Registers

Table 7-76 lists the memory-mapped registers for the TAA5412-Q1 registers. All register offset addresses not listed in Table 7-76 should be considered as reserved locations and the register contents should not be modified.

Table 7-76 TAA5412-Q1 Registers

Address	Acronym	Register Name	Reset Value	Section
0x0	PAGE_CFG	Device page register	0x00	PAGE_CFG Register (Address = 0x0) [Reset = 0x00]
0x3	DSP_CFG0		0x00	DSP_CFG0 Register (Address = 0x3) [Reset = 0x00]
0xD	CLK_CFG0		0x00	CLK_CFG0 Register (Address = 0xD) [Reset = 0x00]
0xE	CHANNEL_CFG1		0x00	CHANNEL_CFG1 Register (Address = 0xE) [Reset = 0x00]
0x17	SRC_CFG0	SRC configuration register 1	0x00	SRC_CFG0 Register (Address = 0x17) [Reset = 0x00]
0x18	SRC_CFG1	SRC configuration register 2	0x00	SRC_CFG1 Register (Address = 0x18) [Reset = 0x00]
0x1E	LPAD_CFG1	LPAD	0x20	LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]
0x20	LPAD_CFG1	LPAD configuration register 1	0x00	LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]
0x24	AGC_DRC_CFG	AGC_DRC configuration register 2	0x00	AGC_DRC_CFG Register (Address = 0x24) [Reset = 0x00]
0x2C	MIXER_CFG0	MISC configuration register 0	0x00	MIXER_CFG0 Register (Address = 0x2C) [Reset = 0x00]
0x2D	MISC_CFG0	MISC configuration register 0	0x00	MISC_CFG0 Register (Address = 0x2D) [Reset = 0x00]
0x2F	INT_MASK0	Interrupt Mask Register-0	0xFF	INT_MASK0 Register (Address = 0x2F) [Reset = 0xFF]
0x30	INT_MASK1	Interrupt Mask Register-1	0x0F	INT_MASK1 Register (Address = 0x30) [Reset = 0x0F]
0x31	INT_MASK2	Interrupt Mask Register-2	0x00	INT_MASK2 Register (Address = 0x31) [Reset = 0x00]
0x32	INT_MASK4	Interrupt Mask Register-3	0x00	INT_MASK4 Register (Address = 0x32) [Reset = 0x00]
0x33	INT_MASK5	Interrupt Mask Register-3	0x30	INT_MASK5 Register (Address = 0x33) [Reset = 0x30]
0x34	INT_LTCH0	Latched Interrupt Readback Register-0	0x00	INT_LTCH0 Register (Address = 0x34) [Reset = 0x00]
0x35	CHx_LTCH	Summary of Diagnostics	0x00	CHx_LTCH Register (Address = 0x35) [Reset = 0x00]
0x36	IN_CH1_LTCH		0x00	IN_CH1_LTCH Register (Address = 0x36) [Reset = 0x00]
0x37	IN_CH2_LTCH		0x00	IN_CH2_LTCH Register (Address = 0x37) [Reset = 0x00]
0x38	ADC_CHx_OVRLD		0x00	ADC_CHx_OVRLD Register (Address = 0x38) [Reset = 0x00]
0x3A	INT_LTCH1	Latched Interrupt Readback Register-0	0x00	INT_LTCH1 Register (Address = 0x3A) [Reset = 0x00]
0x3B	INT_LTCH2	Latched Interrupt Readback Register-3	0x00	INT_LTCH2 Register (Address = 0x3B) [Reset = 0x00]
0x3C	INT_LIVE0	Live Interrupt Readback Register-0	0x00	INT_LIVE0 Register (Address = 0x3C) [Reset = 0x00]
0x3D	CHx_LIVE	Summary of Diagnostics	0x00	CHx_LIVE Register (Address = 0x3D) [Reset = 0x00]
0x3E	IN_CH1_LIVE		0x00	IN_CH1_LIVE Register (Address = 0x3E) [Reset = 0x00]
0x3F	IN_CH2_LIVE		0x00	IN_CH2_LIVE Register (Address = 0x3F) [Reset = 0x00]
0x42	INT_LIVE1	Latched Interrupt Readback Register-0	0x00	INT_LIVE1 Register (Address = 0x42) [Reset = 0x00]
0x43	INT_LIVE2	Latched Interrupt Readback Register-3	0x00	INT_LIVE2 Register (Address = 0x43) [Reset = 0x00]
0x46	DIAG_CFG0		0x00	DIAG_CFG0 Register (Address = 0x46) [Reset = 0x00]
0x47	DIAG_CFG1		0x37	DIAG_CFG1 Register (Address = 0x47) [Reset = 0x37]
0x48	DIAG_CFG2		0x87	DIAG_CFG2 Register (Address = 0x48) [Reset = 0x87]
0x4A	DIAG_CFG4		0xB8	DIAG_CFG4 Register (Address = 0x4A) [Reset = 0xB8]
0x4B	DIAG_CFG5		0x00	DIAG_CFG5 Register (Address = 0x4B) [Reset = 0x00]
0x4C	DIAG_CFG6		0xA2	DIAG_CFG6 Register (Address = 0x4C) [Reset = 0xA2]
0x4D	DIAG_CFG7		0x48	DIAG_CFG7 Register (Address = 0x4D) [Reset = 0x48]
0x4E	DIAG_CFG8		0xBA	DIAG_CFG8 Register (Address = 0x4E) [Reset = 0xBA]
0x4F	DIAG_CFG9		0x4B	DIAG_CFG9 Register (Address = 0x4F) [Reset = 0x4B]
0x50	DIAG_CFG10		0x88	DIAG_CFG10 Register (Address = 0x50) [Reset = 0x88]
0x51	DIAG_CFG11		0x40	DIAG_CFG11 Register (Address = 0x51) [Reset = 0x40]
0x52	DIAG_CFG12		0x44	DIAG_CFG12 Register (Address = 0x52) [Reset = 0x44]
0x53	DIAG_CFG13		0x00	DIAG_CFG13 Register (Address = 0x53) [Reset = 0x00]
0x54	DIAG_CFG14		0x48	DIAG_CFG14 Register (Address = 0x54) [Reset = 0x48]
0x56	DIAG_MON_MSB_VBAT		0x00	DIAG_MON_MSB_VBAT Register (Address = 0x56) [Reset = 0x00]
0x57	DIAG_MON_LSB_VBAT		0x00	DIAG_MON_LSB_VBAT Register (Address = 0x57) [Reset = 0x00]
0x58	DIAG_MON_MSB_MBIAS		0x00	DIAG_MON_MSB_MBIAS Register (Address = 0x58) [Reset = 0x00]
0x59	DIAG_MON_LSB_MBIAS		0x01	DIAG_MON_LSB_MBIAS Register (Address = 0x59) [Reset = 0x01]
0x5A	DIAG_MON_MSB_IN1P		0x00	DIAG_MON_MSB_IN1P Register (Address = 0x5A) [Reset = 0x00]
0x5B	DIAG_MON_LSB_IN1P		0x02	DIAG_MON_LSB_IN1P Register (Address = 0x5B) [Reset = 0x02]
0x5C	DIAG_MON_MSB_IN1M		0x00	DIAG_MON_MSB_IN1M Register (Address = 0x5C) [Reset = 0x00]
0x5D	DIAG_MON_LSB_IN1M		0x03	DIAG_MON_LSB_IN1M Register (Address = 0x5D) [Reset = 0x03]
0x5E	DIAG_MON_MSB_IN2P		0x00	DIAG_MON_MSB_IN2P Register (Address = 0x5E) [Reset = 0x00]
0x5F	DIAG_MON_LSB_IN2P		0x04	DIAG_MON_LSB_IN2P Register (Address = 0x5F) [Reset = 0x04]
0x60	DIAG_MON_MSB_IN2M		0x00	DIAG_MON_MSB_IN2M Register (Address = 0x60) [Reset = 0x00]
0x61	DIAG_MON_LSB_IN2M		0x05	DIAG_MON_LSB_IN2M Register (Address = 0x61) [Reset = 0x05]
0x6A	DIAG_MON_MSB_TEMP		0x00	DIAG_MON_MSB_TEMP Register (Address = 0x6A) [Reset = 0x00]
0x6B	DIAG_MON_LSB_TEMP		0x0A	DIAG_MON_LSB_TEMP Register (Address = 0x6B) [Reset = 0x0A]
0x6C	DIAG_MON_MSB_MBIAS_LOAD		0x00	DIAG_MON_MSB_MBIAS_LOAD Register (Address = 0x6C) [Reset = 0x00]
0x6D	DIAG_MON_LSB_MBIAS_LOAD		0x0B	DIAG_MON_LSB_MBIAS_LOAD Register (Address = 0x6D) [Reset = 0x0B]
0x6E	DIAG_MON_MSB_AVDD		0x00	DIAG_MON_MSB_AVDD Register (Address = 0x6E) [Reset = 0x00]
0x6F	DIAG_MON_LSB_AVDD		0x0C	DIAG_MON_LSB_AVDD Register (Address = 0x6F) [Reset = 0x0C]
0x70	DIAG_MON_MSB_GPA		0x00	DIAG_MON_MSB_GPA Register (Address = 0x70) [Reset = 0x00]
0x71	DIAG_MON_LSB_GPA		0x0D	DIAG_MON_LSB_GPA Register (Address = 0x71) [Reset = 0x0D]
0x72	BOOST_CFG		0x00	BOOST_CFG Register (Address = 0x72) [Reset = 0x00]
0x73	MICBIAS_CFG		0xA0	MICBIAS_CFG Register (Address = 0x73) [Reset = 0xA0]

7.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 7-77.

Return to the Summary Table.

The device memory map is divided into pages. This register sets the page.

Table 7-77 PAGE_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PAGE[7:0]	R/W	00000000b	These bits set the device page. 0d = Page 0 1d = Page 1 2d to 254d = Page 2 to page 254 respectively 255d = Page 255

7.2.2 DSP_CFG0 Register (Address = 0x3) [Reset = 0x00]

DSP_CFG0 is shown in Table 7-78.

Return to the Summary Table.

Table 7-78 DSP_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0b	Reserved bit; Write only reset value
6	RESERVED	R/W	0b	Reserved bit; Write only reset value
5	RESERVED	R/W	0b	Reserved bit; Write only reset value
4	RESERVED	R	0b	Reserved bit; Write only reset value
3	RESERVED	R/W	0b	Reserved bit; Write only reset value
2	RESERVED	R/W	0b	Reserved bit; Write only reset value
1	DIS_DVOL_OTF_CHG	R/W	0b	Disable run-time changes to DVOL settings. 0d = Digital volume control changes supported while ADC is powered-on 1d = Digital volume control changes not supported while ADC is powered-on. This is useful for 384 kHz and higher sample rate if more than one channel processing is required.
0	EN_BQ_OTF_CHG	R/W	0b	Enable run-time changes to Biquad settings. 0d = Disable on the fly biquad changes 1d = Enable on the fly biquad changes

7.2.3 CLK_CFG0 Register (Address = 0xD) [Reset = 0x00]

CLK_CFG0 is shown in Table 7-79.

Return to the Summary Table.

Table 7-79 CLK_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CNT_TGT_CFG_OVR_PASI	R/W	0b	ASI controller target Config Override Register 0d = controller-target Config as per PASI_CNT_CFG bit. 1d = Override the standard behavior of the PASI_CNT_CFG. In this case the clock auto detect feature is not available. PASI_CNT_CFG = 0 : BCLK is input but FSYNC is output. PASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
6	CNT_TGT_CFG_OVR_SASI	R/W	0b	ASI controller target Config Override Register 0d = controller-target Config as per SASI_CNT_CFG bit. 1d = Override the standard behavior of the SASI_CNT_CFG. In this case the clock auto detect feature is not available. SASI_CNT_CFG = 0 : BCLK is input but FSYNC is output. SASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
5	RESERVED	R	0b	Reserved bit; Write only reset value
4-3	RESERVED	R/W	00b	Reserved bits; Write only reset values
2	PASI_USE_INT_FSYNC	R/W	0b	For Primary use internal FSYNC in controller mode configuration. 0d = Use external FSYNC 1d = Use internal FSYNC
1	SASI_USE_INT_FSYNC	R/W	0b	For Secondary use internal FSYNC in controller mode configuration. 0d = Use external FSYNC 1d = Use internal FSYNC
0	RESERVED	R/W	0b	Reserved bit; Write only reset value

7.2.4 CHANNEL_CFG1 Register (Address = 0xE) [Reset = 0x00]

CHANNEL_CFG1 is shown in Table 7-80.

Return to the Summary Table.

Table 7-80 CHANNEL_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FORCE_DYN_MODE_CUST_MAX_CH	R/W	0b	ADC Force dynamic mode custom max channel 0d = In Dynamic, Max channel is based on ADC_DYN_MAXCH_SEL 1d = In Dynamic mode, max channel is custom as DYN_MODE_CUST_MAX_CH
6-3	DYN_MODE_CUST_MAX_CH[3:0]	R/W	0000b	ADC Dynamic mode custom max channel configuration [3]->CH4_EN [2]->CH3_EN [1]->CH2_EN [0]->CH1_EN
2-0	RESERVED	R	000b	Reserved bits; Write only reset values

7.2.5 SRC_CFG0 Register (Address = 0x17) [Reset = 0x00]

SRC_CFG0 is shown in Table 7-81.

Return to the Summary Table.

This register is configuration register 1 for SRC.

Table 7-81 SRC_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SRC_EN	R/W	0b	SRC enable config 0b = SRC disable 1b = SRC enable
6	DIS_AUTO_SRC_DET	R/W	0b	SRC auto detect config 0b = SRC auto detect enabled 1b = SRC auto detect disabled
5-0	RESERVED	R	000000b	Reserved bits; Write only reset value

7.2.6 SRC_CFG1 Register (Address = 0x18) [Reset = 0x00]

SRC_CFG1 is shown in Table 7-82.

Return to the Summary Table.

This register is configuration register 2 for SRC.

Table 7-82 SRC_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MAIN_FS_CUSTOM_CFG	R/W	0b	Main Fs custom config 0b = Main Fs is auto inferred 1b = Main Fs need to be selected from MAIN_FS_SELECT_CFG
6	MAIN_FS_SELECT_CFG	R/W	0b	Main Fs select config 0b = PASI Fs shall be used as Main Fs 1b = SASI Fs shall be used as Main Fs
5-3	MAIN_AUX_RATIO_M_CUSTOM_CFG[2:0]	R/W	000b	Main and Aux Fs Ratio m:n config 0d = m is auto inferred 1d = 1 2d = 2 3d = 3 4d = 4 5d = Reserved 6d = 6 7d = Reserved
2-0	MAIN_AUX_RATIO_N_CUSTOM_CFG[2:0]	R/W	000b	Main and Aux Fs Ratio m:n config 0d = n is auto inferred 1d = 1 2d = 2 3d = 3 4d = 4 5d = Reserved 6d = 6 7d = Reserved

7.2.7 LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]

LPAD_CFG1 is shown in Table 7-83.

Return to the Summary Table.

Low Power Activity Detection. Voice activity detection or Ultrasonic Activity detection configuration register 1

Table 7-83 LPAD_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	LPAD_MODE[1:0]	R/W	00b	Auto ADC power up / power down configuration selection. 0d = User initiated ADC power-up and ADC power-down 1d = VAD/UAD interrupt based ADC power up and ADC power down 2d = VAD/UAD interrupt based ADC power up but user initiated ADC power down Dont use
5-4	LPAD_CH_SEL[1:0]	R/W	10b	VAD channel select. 0d = Channel 1 is monitored for VAD/UAD activity 1d = Channel 2 is monitored for VAD/UAD activity 2d = Channel 3 is monitored for VAD/UAD activity 3d = Channel 4 is monitored for VAD/UAD activity
3	LPAD_SDOUT_INT_CFG	R/W	0b	SDOUT interrupt configuration. 0d = SDOUT pin is not enabled for interrupt function 1d = SDOUT pin is enabled to support interrupt output when channel data in not being recorded
2	RESERVED	R	0b	Reserved bit; Write only reset value
1	LPAD_PD_DET_EN	R/W	0b	Enable ASI output data during VAD/UAD activity. 0d = VAD/UAD processing is not enabled during ADC recording 1d = VAD/UAD processing is enabled during ADC recording and VAD interrupts are generated as configured
0	RESERVED	R/W	0b	Reserved bit; Write only reset value

7.2.8 AGC_DRC_CFG Register (Address = 0x24) [Reset = 0x00]

AGC_DRC_CFG is shown in Table 7-84.

Return to the Summary Table.

This register is configuration register 2 for AGC_DRC.

Table 7-84 AGC_DRC_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	AGC_CH1_EN	R/W	0b	AGC Channel 1 enable config 0d = disable 1d = enable
6	AGC_CH2_EN	R/W	0b	AGC Channel 2 enable config 0d = disable 1d = enable
5	AGC_CH3_EN	R/W	0b	AGC Channel 3 enable config 0d = disable 1d = enable
4	AGC_CH4_EN	R/W	0b	AGC Channel 4 enable config 0d = disable 1d = enable
3	DRC_CH1_EN	R/W	0b	DRC Channel 1 enable config 0d = disable 1d = enable
2	DRC_CH2_EN	R/W	0b	DRC Channel 2 enable config 0d = disable 1d = enable
1	DRC_CH3_EN	R/W	0b	DRC Channel 3 enable config 0d = disable 1d = enable
0	DRC_CH4_EN	R/W	0b	DRC Channel 4 enable config 0d = disable 1d = enable

7.2.9 MIXER_CFG0 Register (Address = 0x2C) [Reset = 0x00]

MIXER_CFG0 is shown in Table 7-85.

Return to the Summary Table.

This register is the MISC configuration register 0.

Table 7-85 MIXER_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0b	Reserved bit; Write only reset value
6	EN_SIDE_CHAIN_MIXER	R/W	0b	Enable Side Chain Mixer 0b = Disabled 1b = Enabled
5	EN_ADC_CHANNEL_MIXER	R/W	0b	Enable ADC Channel Mixer 0b = Disabled 1b = Enabled
4	RESERVED	R/W	0b	Reserved bit; Write only reset value
3-0	RESERVED	R	0000b	Reserved bits; Write only reset values

7.2.10 MISC_CFG0 Register (Address = 0x2D) [Reset = 0x00]

MISC_CFG0 is shown in Table 7-86.

Return to the Summary Table.

This register is the MISC configuration register 0.

Table 7-86 MISC_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0b	Reserved bit; Write only reset value
6	RESERVED	R/W	0b	Reserved bit; Write only reset value
5	RESERVED	R/W	0b	Reserved bit; Write only reset value
4	EN_DRC	R/W	0b	DRC enable config 0b = DRC disable 1b = DRC enable
3	RESERVED	R/W	0b	Reserved bit; Write only reset value
2	RESERVED	R/W	0b	Reserved bit; Write only reset value
1	DSP_VBAT_AVDD_SEL	R/W	0b	SAR data source select for DSP Limiter, BOP, DRC 0b = SAR VBAT data to DSP 1b = SAR AVDD data to DSP
0	RESERVED	R/W	0b	Reserved bit; Write only reset value

7.2.11 INT_MASK0 Register (Address = 0x2F) [Reset = 0xFF]

INT_MASK0 is shown in Table 7-87.

Return to the Summary Table.

Interrupt masks.

Table 7-87 INT_MASK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK0	R/W	1b	Clock error interrupt mask. 0b = Don't Mask 1b = Mask
6	INT_MASK0	R/W	1b	PLL Lock interrupt mask. 0b = Don't Mask 1b = Mask
5	INT_MASK0	R/W	1b	Boost Over Temperature interrupt mask. 0b = Don't Mask 1b = Mask
4	INT_MASK0	R/W	1b	Boost Over Current interrupt mask. 0b = Don't Mask 1b = Mask
3	INT_MASK0	R/W	1b	Boost MO interrupt mask. 0b = Don't Mask 1b = Mask
2	RESERVED	R/W	1b	Reserved bit; Write only reset value
1	RESERVED	R/W	1b	Reserved bit; Write only reset value
0	RESERVED	R/W	1b	Reserved bit; Write only reset value

7.2.12 INT_MASK1 Register (Address = 0x30) [Reset = 0x0F]

INT_MASK1 is shown in Table 7-88.

Return to the Summary Table.

Interrupt masks.

Table 7-88 INT_MASK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK1	R/W	0b	Channel-1 Input DC Faults Diagnostic Interrupt Mask. 0b = Don't Mask 1b = Mask
6	INT_MASK1	R/W	0b	Channel-2 Input DC Faults Diagnostic Interrupt Mask. 0b = Don't Mask 1b = Mask
5	INT_MASK1	R/W	0b	Channel-1 Output DC Faults Diagnostic Interrupt Mask. 0b = Don't Mask 1b = Mask
4	INT_MASK1	R/W	0b	Channel-2 Output DC Faults Diagnostic Interrupt Mask. 0b = Don't Mask 1b = Mask
3	INT_MASK1	R/W	1b	Input Faults Diagnostic Interrupt Mask for "Short to VBAT_IN" detect when VBAT_IN Voltage is less than MICBIAS Voltage. 0b = Don't Mask 1b = Mask
2	RESERVED	R/W	1b	Reserved bit; Write only reset value
1	RESERVED	R/W	1b	Reserved bit; Write only reset value
0	RESERVED	R/W	1b	Reserved bit; Write only reset value

7.2.13 INT_MASK2 Register (Address = 0x31) [Reset = 0x00]

INT_MASK2 is shown in Table 7-89.

Return to the Summary Table.

Interrupt masks.

Table 7-89 INT_MASK2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK2	R/W	0b	Input Diagnostics - Open Inputs Fault Interrupt Mask. 0b = Don't Mask 1b = Mask
6	INT_MASK2	R/W	0b	Input Diagnostics - Inputs Shorted Fault Interrupt Mask. 0b = Don't Mask 1b = Mask
5	INT_MASK2	R/W	0b	Input Diagnostics - INP Shorted to GND Fault Interrupt Mask. 0b = Don't Mask 1b = Mask
4	INT_MASK2	R/W	0b	Input Diagnostics - INM Shorted to GND Fault Interrupt Mask. 0b = Don't Mask 1b = Mask
3	INT_MASK2	R/W	0b	Input Diagnostics - INP Shorted to MICBIAS Fault Interrupt Mask. 0b = Don't Mask 1b = Mask
2	INT_MASK2	R/W	0b	Input Diagnostics - INM Shorted to MICBIAS Fault Interrupt Mask. 0b = Don't Mask 1b = Mask
1	INT_MASK2	R/W	0b	Input Diagnostics - INP Shorted to VBAT_IN Fault Interrupt Mask. 0b = Don't Mask 1b = Mask
0	INT_MASK2	R/W	0b	Input Diagnostics - INM Shorted to VBAT_IN Fault Interrupt Mask. 0b = Don't Mask 1b = Mask

7.2.14 INT_MASK4 Register (Address = 0x32) [Reset = 0x00]

INT_MASK4 is shown in Table 7-90.

Return to the Summary Table.

Interrupt masks.

Table 7-90 INT_MASK4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK4	R/W	0b	INP overvoltage fault mask. 0b = Don't Mask 1b = Mask
6	INT_MASK4	R/W	0b	INM overvoltage fault mask. 0b = Don't Mask 1b = Mask
5	RESERVED	R/W	0b	Reserved bit; Write only reset value
4	RESERVED	R/W	0b	Reserved bit; Write only reset value
3	RESERVED	R/W	0b	Reserved bit; Write only reset value
2	RESERVED	R/W	0b	Reserved bit; Write only reset value
1	RESERVED	R/W	0b	Reserved bit; Write only reset value
0	RESERVED	R/W	0b	Reserved bit; Write only reset value

7.2.15 INT_MASK5 Register (Address = 0x33) [Reset = 0x30]

INT_MASK5 is shown in Table 7-91.

Return to the Summary Table.

Interrupt masks.

Table 7-91 INT_MASK5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK5	R/W	0b	GPA up threshold fault mask. 0b = Don't Mask 1b = Mask
6	INT_MASK5	R/W	0b	GPA low threshold fault mask. 0b = Don't Mask 1b = Mask
5	INT_MASK5	R/W	1b	VAD power up detect interrupt mask. 0b = Don't Mask 1b = Mask
4	INT_MASK5	R/W	1b	VAD power down detect interrupt mask. 0b = Don't Mask 1b = Mask
3	INT_MASK5	R/W	0b	Micbias short circuit fault mask. 0b = Don't Mask 1b = Mask
2	INT_MASK5	R/W	0b	Micbias High current fault mask. 0b = Don't Mask 1b = Mask
1	INT_MASK5	R/W	0b	Micbias Low current fault mask. 0b = Don't Mask 1b = Mask
0	INT_MASK5	R/W	0b	Micbias Over voltage fault mask. 0b = Don't Mask 1b = Mask

7.2.16 INT_LTCH0 Register (Address = 0x34) [Reset = 0x00]

INT_LTCH0 is shown in Table 7-92.

Return to the Summary Table.

Latched interrupt readback.

Table 7-92 INT_LTCH0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH0	R	0b	Interrupt due to clock error (self clearing bit). 0b = No interrupt 1b = Interrupt
6	INT_LTCH0	R	0b	Interrupt due to PLL Lock (self clearing bit) 0b = No interrupt 1b = Interrupt
5	INT_LTCH0	R	0b	Interrupt due to Boost Over Temperature (self clearing bit). 0b = No interrupt 1b = Interrupt
4	INT_LTCH0	R	0b	Interrupt due to Boost Over Current.(self clearing bit). 0b = No interrupt 1b = Interrupt
3	INT_LTCH0	R	0b	Interrupt due to Boost MO. (self clearing bit). 0b = No interrupt 1b = Interrupt
2	RESERVED	R	0b	Reserved bit; Write only reset value
1	RESERVED	R	0b	Reserved bit; Write only reset value
0	RESERVED	R	0b	Reserved bit; Write only reset value

7.2.17 CHx_LTCH Register (Address = 0x35) [Reset = 0x00]

CHx_LTCH is shown in Table 7-93.

Return to the Summary Table.

Channel level Diagnostics Latched Status

Table 7-93 CHx_LTCH Register Field Descriptions

Bit	Field	Type	Reset	Description
7	STS_CHx_LTCH	R	0b	Status of Input CH1_LTCH. 0b = No faults occurred in input channel 1 1b = Fault or Faults have occurred in input channel 1
6	STS_CHx_LTCH	R	0b	Status of Input CH2_LTCH. 0b = No faults occurred in input channel 2 1b = Fault or Faults have occurred in input channel 2
5	STS_CHx_LTCH	R	0b	Status of Output CH1_LTCH. 0b = No faults occurred in output channel 1 1b = Fault or Faults have occurred in output channel 1
4	STS_CHx_LTCH	R	0b	Status of Output CH2_LTCH. 0b = No faults occurred in output channel 2 1b = Fault or Faults have occurred in output channel 2
3	STS_CHx_LTCH	R	0b	Status on fault due "Short to VBAT_IN fault detected when VBAT_IN is less than MICBIAS" 0b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS did NOT occur in any channel 1b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has occurred in atleast one channel
2	RESERVED	R	0b	Reserved bit; Write only reset value
1	RESERVED	R	0b	Reserved bit; Write only reset value
0	RESERVED	R	0b	Reserved bit; Write only reset value

7.2.18 IN_CH1_LTCH Register (Address = 0x36) [Reset = 0x00]

IN_CH1_LTCH is shown in Table 7-94.

Return to the Summary Table.

Table 7-94 IN_CH1_LTCH Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IN_CH1_LTCH	R	0b	Input Channel-1 Open Inputs (self clearing bit). 0b = No Open Inputs 1b = Open Inputs
6	IN_CH1_LTCH	R	0b	Input Channel-1 Inputs Shorted (self clearing bit). 0b = No Input Shorted 1b = Input Shorted each Other
5	IN_CH1_LTCH	R	0b	Input Channel-1 INP Shorted to GND (self clearing bit). 0b = INP not shorted to GND 1b = INP shorted to GND
4	IN_CH1_LTCH	R	0b	Input Channel-1 INM Shorted to GND (self clearing bit). 0b = INM not shorted to GND 1b = INM shorted to GND
3	IN_CH1_LTCH	R	0b	Input Channel-1 INP Shorted to MICBIAS (self clearing bit). 0b = INP not shorted to MICBIAS 1b = INP shorted to MICBIAS
2	IN_CH1_LTCH	R	0b	Input Channel-1 INM Shorted to MICBIAS (self clearing bit). 0b = INM not shorted to MICBIAS 1b = INM shorted to MICBIAS
1	IN_CH1_LTCH	R	0b	Input Channel-1 INP Shorted to VBAT_IN (self clearing bit). 0b = INP not shorted to VBAT_IN 1b = INP shorted to VBAT_IN
0	IN_CH1_LTCH	R	0b	Input Channel-1 INM Shorted to VBAT_IN (self clearing bit). 0b = INM not shorted to VBAT_IN 1b = INM shorted to VBAT_IN

7.2.19 IN_CH2_LTCH Register (Address = 0x37) [Reset = 0x00]

IN_CH2_LTCH is shown in Table 7-95.

Return to the Summary Table.

Table 7-95 IN_CH2_LTCH Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IN_CH2_LTCH	R	0b	Input Channel-2 Open Inputs (self clearing bit). 0b = No Open Inputs 1b = Open Inputs
6	IN_CH2_LTCH	R	0b	Input Channel-2 Inputs Shorted (self clearing bit). 0b = No Input Shorted 1b = Input Shorted each Other
5	IN_CH2_LTCH	R	0b	Input Channel-2 INP Shorted to GND (self clearing bit). 0b = INP not shorted to GND 1b = INP shorted to GND
4	IN_CH2_LTCH	R	0b	Input Channel-2 INM Shorted to GND (self clearing bit). 0b = INM not shorted to GND 1b = INM shorted to GND
3	IN_CH2_LTCH	R	0b	Input Channel-2 INP Shorted to MICBIAS (self clearing bit). 0b = INP not shorted to MICBIAS 1b = INP shorted to MICBIAS
2	IN_CH2_LTCH	R	0b	Input Channel-2 INM Shorted to MICBIAS (self clearing bit). 0b = INM not shorted to MICBIAS 1b = INM shorted to MICBIAS
1	IN_CH2_LTCH	R	0b	Input Channel-2 INP Shorted to VBAT_IN (self clearing bit). 0b = INP not shorted to VBAT_IN 1b = INP shorted to VBAT_IN
0	IN_CH2_LTCH	R	0b	Input Channel-2 INM Shorted to VBAT_IN (self clearing bit). 0b = INM not shorted to VBAT_IN 1b = INM shorted to VBAT_IN

7.2.20 ADC_CHx_OVRLD Register (Address = 0x38) [Reset = 0x00]

ADC_CHx_OVRLD is shown in Table 7-96.

Return to the Summary Table.

Table 7-96 ADC_CHx_OVRLD Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved bit; Write only reset value
6	RESERVED	R	0b	Reserved bit; Write only reset value
5	RESERVED	R	0b	Reserved bit; Write only reset value
4	RESERVED	R	0b	Reserved bit; Write only reset value
3	MASK_ADC_CH1_OVRLD_FLAG	R/W	0b	ADC CH1 OVRLD fault mask. 0b = Don't Mask 1b = Mask
2	MASK_ADC_CH2_OVRLD_FLAG	R/W	0b	ADC CH2 OVRLD fault mask. 0b = Don't Mask 1b = Mask
1-0	RESERVED	R	00b	Reserved bits; Write only reset value

7.2.21 INT_LTCH1 Register (Address = 0x3A) [Reset = 0x00]

INT_LTCH1 is shown in Table 7-97.

Return to the Summary Table.

Latched interrupt readback.

Table 7-97 INT_LTCH1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH1	R	0b	Channel-1 INP Over Voltage (self clearing bit). 0b = No INP Over Voltage fault 1b = INP Over Voltage fault has occured
6	INT_LTCH1	R	0b	Channel-1 INM Over Voltage (self clearing bit). 0b = No INM Over Voltage fault 1b = INM Over Voltage fault has occured
5	INT_LTCH1	R	0b	Channel-2 INP Over Voltage (self clearing bit). 0b = No INP Over Voltage fault 1b = INP Over Voltage fault has occured
4	INT_LTCH1	R	0b	Channel-2 INM Over Voltage (self clearing bit). 0b = No INM Over Voltage fault 1b = INM Over Voltage fault has occured
3	INT_LTCH1	R	0b	Interrupt due to Headset Insert Detection (self clearing bit). 0b = No interrupt 1b = Interrupt
2	INT_LTCH1	R	0b	Interrupt due to Headset Remove Detection (self clearing bit). 0b = No interrupt 1b = Interrupt
1	INT_LTCH1	R	0b	Interrupt due to Headset hook(button) (self clearing bit). 0b = No interrupt 1b = Interrupt
0	INT_LTCH1	R	0b	Interrupt due to MIPS overload (self clearing bit) 0b = No interrupt 1b = Interrupt

7.2.22 INT_LTCH2 Register (Address = 0x3B) [Reset = 0x00]

INT_LTCH2 is shown in Table 7-98.

Return to the Summary Table.

Latched interrupt readback.

Table 7-98 INT_LTCH2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH2	R	0b	Interrupt due to GPA up threshold fault (self clearing bit). 0b = No interrupt 1b = Interrupt
6	INT_LTCH2	R	0b	Interrupt due to GPA low threshold fault (self clearing bit) 0b = No interrupt 1b = Interrupt
5	INT_LTCH2	R	0b	Interrupt due to VAD power up detect (self clearing bit). 0b = No interrupt 1b = Interrupt
4	INT_LTCH2	R	0b	Interrupt due to VAD power down detect (self clearing bit). 0b = No interrupt 1b = Interrupt
3	INT_LTCH2	R	0b	Interrupt due to Micbias short circuit condition (self clearing bit) 0b = No interrupt 1b = Interrupt
2	INT_LTCH2	R	0b	Interrupt due to Micbias High current fault (self clearing bit). 0b = No interrupt 1b = Interrupt
1	INT_LTCH2	R	0b	Interrupt due to Micbias Low current fault (self clearing bit) 0b = No interrupt 1b = Interrupt
0	INT_LTCH2	R	0b	Interrupt due to Micbias Over voltage fault (self clearing bit). 0b = No interrupt 1b = Interrupt

7.2.23 INT_LIVE0 Register (Address = 0x3C) [Reset = 0x00]

INT_LIVE0 is shown in Table 7-99.

Return to the Summary Table.

Latched interrupt readback.

Table 7-99 INT_LIVE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LIVE0	R	0b	Interrupt due to clock error . 0b = No interrupt 1b = Interrupt
6	INT_LIVE0	R	0b	Interrupt due to PLL Lock 0b = No interrupt 1b = Interrupt
5	INT_LIVE0	R	0b	Interrupt due to Boost Over Temperature . 0b = No interrupt 1b = Interrupt
4	INT_LIVE0	R	0b	Interrupt due to Boost Over Current.. 0b = No interrupt 1b = Interrupt
3	INT_LIVE0	R	0b	Interrupt due to Boost MO. . 0b = No interrupt 1b = Interrupt
2	RESERVED	R	0b	Reserved bit; Write only reset value
1	RESERVED	R	0b	Reserved bit; Write only reset value
0	RESERVED	R	0b	Reserved bit; Write only reset value

7.2.24 CHx_LIVE Register (Address = 0x3D) [Reset = 0x00]

CHx_LIVE is shown in Table 7-100.

Return to the Summary Table.

Channel level Diagnostics Live Status

Table 7-100 CHx_LIVE Register Field Descriptions

Bit	Field	Type	Reset	Description
7	STS_CHx_LIVE	R	0b	Status of Input CH1_LIVE. 0b = No faults occurred in input channel 1 1b = Fault or Faults have occurred in input channel 1
6	STS_CHx_LIVE	R	0b	Status of Input CH2_LIVE. 0b = No faults occurred in input channel 2 1b = Fault or Faults have occurred in input channel 2
5	STS_CHx_LIVE	R	0b	Status of Output CH1_LIVE. 0b = No faults occurred in output channel 1 1b = Fault or Faults have occurred in output channel 1
4	STS_CHx_LIVE	R	0b	Status of Output CH2_LIVE. 0b = No faults occurred in output channel 2 1b = Fault or Faults have occurred in output channel 2
3	STS_CHx_LIVE	R	0b	Status on fault due "Short to VBAT_IN fault detected when VBAT_IN is less than MICBIAS" 0b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS did NOT occur in any channel 1b = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has occurred in atleast one channel
2	RESERVED	R	0b	Reserved bit; Write only reset value
1	RESERVED	R	0b	Reserved bit; Write only reset value
0	RESERVED	R	0b	Reserved bit; Write only reset value

7.2.25 IN_CH1_LIVE Register (Address = 0x3E) [Reset = 0x00]

IN_CH1_LIVE is shown in Table 7-101.

Return to the Summary Table.

Table 7-101 IN_CH1_LIVE Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IN_CH1_LIVE	R	0b	Input Channel-1 Open Inputs . 0b = No Open Inputs 1b = Open Inputs
6	IN_CH1_LIVE	R	0b	Input Channel-1 Inputs Shorted . 0b = No Input Shorted 1b = Input Shorted each Other
5	IN_CH1_LIVE	R	0b	Input Channel-1 INP Shorted to GND . 0b = INP not shorted to GND 1b = INP shorted to GND
4	IN_CH1_LIVE	R	0b	Input Channel-1 INM Shorted to GND . 0b = INM not shorted to GND 1b = INM shorted to GND
3	IN_CH1_LIVE	R	0b	Input Channel-1 INP Shorted to MICBIAS . 0b = INP not shorted to MICBIAS 1b = INP shorted to MICBIAS
2	IN_CH1_LIVE	R	0b	Input Channel-1 INM Shorted to MICBIAS . 0b = INM not shorted to MICBIAS 1b = INM shorted to MICBIAS
1	IN_CH1_LIVE	R	0b	Input Channel-1 INP Shorted to VBAT_IN . 0b = INP not shorted to VBAT_IN 1b = INP shorted to VBAT_IN
0	IN_CH1_LIVE	R	0b	Input Channel-1 INM Shorted to VBAT_IN . 0b = INM not shorted to VBAT_IN 1b = INM shorted to VBAT_IN

7.2.26 IN_CH2_LIVE Register (Address = 0x3F) [Reset = 0x00]

IN_CH2_LIVE is shown in Table 7-102.

Return to the Summary Table.

Table 7-102 IN_CH2_LIVE Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IN_CH2_LIVE	R	0b	Input Channel-2 Open Inputs . 0b = No Open Inputs 1b = Open Inputs
6	IN_CH2_LIVE	R	0b	Input Channel-2 Inputs Shorted . 0b = No Input Shorted 1b = Input Shorted each Other
5	IN_CH2_LIVE	R	0b	Input Channel-2 INP Shorted to GND . 0b = INP not shorted to GND 1b = INP shorted to GND
4	IN_CH2_LIVE	R	0b	Input Channel-2 INM Shorted to GND . 0b = INM not shorted to GND 1b = INM shorted to GND
3	IN_CH2_LIVE	R	0b	Input Channel-2 INP Shorted to MICBIAS . 0b = INP not shorted to MICBIAS 1b = INP shorted to MICBIAS
2	IN_CH2_LIVE	R	0b	Input Channel-2 INM Shorted to MICBIAS . 0b = INM not shorted to MICBIAS 1b = INM shorted to MICBIAS
1	IN_CH2_LIVE	R	0b	Input Channel-2 INP Shorted to VBAT_IN . 0b = INP not shorted to VBAT_IN 1b = INP shorted to VBAT_IN
0	IN_CH2_LIVE	R	0b	Input Channel-2 INM Shorted to VBAT_IN . 0b = INM not shorted to VBAT_IN 1b = INM shorted to VBAT_IN

7.2.27 INT_LIVE1 Register (Address = 0x42) [Reset = 0x00]

INT_LIVE1 is shown in Table 7-103.

Return to the Summary Table.

Live interrupt readback.

Table 7-103 INT_LIVE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LIVE1	R	0b	Channel-1 INP Over Voltage . 0b = No INP Over Voltage fault 1b = INP Over Voltage fault has occured
6	INT_LIVE1	R	0b	Channel-1 INM Over Voltage . 0b = No INM Over Voltage fault 1b = INM Over Voltage fault has occured
5	INT_LIVE1	R	0b	Channel-2 INP Over Voltage . 0b = No INP Over Voltage fault 1b = INP Over Voltage fault has occured
4	INT_LIVE1	R	0b	Channel-2 INM Over Voltage . 0b = No INM Over Voltage fault 1b = INM Over Voltage fault has occured
3	RESERVED	R	0b	Reserved bit; Write only reset value
2	RESERVED	R	0b	Reserved bit; Write only reset value
2	RESERVED	R	0b	Reserved bit; Write only reset value
1	RESERVED	R	0b	Reserved bit; Write only reset value
0	RESERVED	R	0b

7.2.28 INT_LIVE2 Register (Address = 0x43) [Reset = 0x00]

INT_LIVE2 is shown in Table 7-104.

Return to the Summary Table.

Live interrupt readback.

Table 7-104 INT_LIVE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LIVE2	R	0b	Interrupt due to GPA up threshold fault . 0b = No interrupt 1b = Interrupt
6	INT_LIVE2	R	0b	Interrupt due to GPA low threshold fault 0b = No interrupt 1b = Interrupt
5	INT_LIVE2	R	0b	Interrupt due to VAD power up detect . 0b = No interrupt 1b = Interrupt
4	INT_LIVE2	R	0b	Interrupt due to VAD power down detect . 0b = No interrupt 1b = Interrupt
3	INT_LIVE2	R	0b	Interrupt due to Micbias short circuit condition 0b = No interrupt 1b = Interrupt
2	INT_LIVE2	R	0b	Interrupt due to Micbias High current fault . 0b = No interrupt 1b = Interrupt
1	INT_LIVE2	R	0b	Interrupt due to Micbias Low current fault 0b = No interrupt 1b = Interrupt
0	INT_LIVE2	R	0b	Interrupt due to Micbias Over voltage fault . 0b = No interrupt 1b = Interrupt

7.2.29 DIAG_CFG0 Register (Address = 0x46) [Reset = 0x00]

DIAG_CFG0 is shown in Table 7-105.

Return to the Summary Table.

Table 7-105 DIAG_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IN_CH1_DIAG_EN	R/W	0b	Channel-1 Input (IN1P and IN1M) Scan for Diagnostics 0b = Diagnostic Disabled 1b = Diagnostic Enabled
6	IN_CH2_DIAG_EN	R/W	0b	Channel-2 Input (IN2P and IN2M) Scan for Diagnostics 0b = Diagnostic Disabled 1b = Diagnostic Enabled
5	INCL_SE_INM	R/W	0b	INxM pin Diagnostics Scan Selection for Single Ended Configuration 0b = INxM pins of single ended channels are excluded for diagnosis 1b = INxM pins of single ended channels are included for diagnosis
4	INCL_AC_COUP	R/W	0b	AC coupled channels pins Scan Selection for Diagnostics 0b = INxP and INxM pins of AC coupled channels are excluded for diagnosis 1b = INxP and INxM pins of AC coupled channels are included for diagnosis
3	RESERVED	R/W	0b	Reserved bit; Write only reset value
2	RESERVED	R/W	0b	Reserved bit; Write only reset value
1	RESERVED	R/W	0b	Reserved bit; Write only reset value
0	RESERVED	R/W	0b	Reserved bit; Write only reset value

7.2.30 DIAG_CFG1 Register (Address = 0x47) [Reset = 0x37]

DIAG_CFG1 is shown in Table 7-106.

Return to the Summary Table.

Table 7-106 DIAG_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_SHT_TERM[3:0]	R/W	0011b	INxP and INxM Terminal Short Detect Threshold 0d = INxP and INxM Terminal Short Detect Threshold Value is 0 mV 1d = INxP and INxM Terminal Short Detect Threshold Value is 30 mV 2d = INxP and INxM Terminal Short Detect Threshold Value is 60 mV 10d to 13d = INxP and INxM Terminal Short Detect Threshold Value is as per configuration 14d = INxP and INxM Terminal Short Detect Threshold Value is 420 mV 15d = INxP and INxM Terminal Short Detect Threshold Value is 450 mV
3-0	DIAG_SHT_VBAT_IN[3:0]	R/W	0111b	Short to VBAT_IN Detect Threshold 0d = Short to VBAT_IN Detect Threshold Value is 0 mV 1d = Short to VBAT_IN Detect Threshold Value is 30 mV 2d = Short to VBAT_IN Detect Threshold Value is 60 mV 10d to 13d = Short to VBAT_IN Detect Threshold Value is as per configuration 14d = Short to VBAT_IN Detect Threshold Value is 420 mV 15d = Short to VBAT_IN Detect Threshold Value is 450 mV

7.2.31 DIAG_CFG2 Register (Address = 0x48) [Reset = 0x87]

DIAG_CFG2 is shown in Table 7-107.

Return to the Summary Table.

Table 7-107 DIAG_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_SHT_GND[3:0]	R/W	1000b	Short to GND Detect Threshold 0d = Short to GND Detect Threshold Value is 0 mV 1d = Short to GND Detect Threshold Value is 60 mV 2d = Short to GND Detect Threshold Value is 120 mV 10d to 13d = Short to GND Detect Threshold Value is as per configuration 14d = Short to GND Detect Threshold Value is 840 mV 15d = Short to GND Detect Threshold Value is 900 mV
3-0	DIAG_SHT_MICBIAS[3:0]	R/W	0111b	Short to MICBIAS Detect Threshold 0d = Short to MICBIAS Detect Threshold Value is 0 mV 1d = Short to MICBIAS Detect Threshold Value is 30 mV 2d = Short to MICBIAS Detect Threshold Value is 60 mV 10d to 13d = Short to MICBIAS Detect Threshold Value is as per configuration 14d = Short to MICBIAS Detect Threshold Value is 420 mV 15d = Short to MICBIAS Detect Threshold Value is 450 mV

7.2.32 DIAG_CFG4 Register (Address = 0x4A) [Reset = 0xB8]

DIAG_CFG4 is shown in Table 7-108.

Return to the Summary Table.

Table 7-108 DIAG_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	REP_RATE[1:0]	R/W	10b	Fault monitoring scan repetition rate 0d = Countinuos back to back scanning of selected channels input pins without any idle time 1d = Fault monitoring repetition rate of 1 ms for selected channels input pins scanning 2d = Fault monitoring repetition rate of 4 ms for selected channels input pins scanning 3d = Fault monitoring repetition rate of 8 ms for selected channels input pins scanning
5-4	RESERVED	R/W	11b	Reserved bits; Write only reset values
3-2	FAULT_DBNCE_SEL[1:0]	R/W	10b	Debounce conut for all the faults (except VBAT_IN short when VBAT_IN < MicBias) 0b = 16 counts for debounce to filter-out false faults detection 1b = 8 counts for debounce to filter-out false faults detection 2b = 4 counts for debounce to filter-out false faults detection 3b = No debounce count
1	VSHORT_DBNCE	R/W	0b	VBAT_IN short debounce count 0b = 16 counts for debounce to filter-out false faults detection 1b = 8 counts for debounce to filter-out false faults detection
0	DIAG_2X_THRES	R/W	0b	Diagostic thresholds range scale 0d = Thresholds same as configrued 1d = All the configruation thresholds gets scale by 2 times

7.2.33 DIAG_CFG5 Register (Address = 0x4B) [Reset = 0x00]

DIAG_CFG5 is shown in Table 7-109.

Return to the Summary Table.

Table 7-109 DIAG_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	DIAG_MOV_AVG_CFG[1:0]	R/W	00b	Moving average configuration 0d = Moving average disabled 1d = Moving average enabled with 0.5 weightage for new and old data 2d = Moving average enabled with 0.75 weightage for old data and 0.25 weightage for new data 3d = Reserved
5	MOV_AVG_DIS_MBIAS_LOAD	R/W	0b	Moving average configuration for MicBias Load channel 0b = Moving average is enabled for Micbias Load channel 1b = Moving average is disabled for Micbias Load channel
4	MOV_AVG_DIS_TEMP_SENS	R/W	0b	Moving average configuration for Temp sense channel 0b = Moving average is enabled for Temp sense channel 1b = Moving average is disabled for Temp sense channel
3	MOV_AVG_DIS_GPA	R/W	0b	Moving average configuration for GPA channel 0b = Moving average is enabled for GPA channel 1b = Moving average is disabled for GPA channel
2-0	RESERVED	R	000b	Reserved bits; Write only reset values

7.2.34 DIAG_CFG6 Register (Address = 0x4C) [Reset = 0xA2]

DIAG_CFG6 is shown in Table 7-110.

Return to the Summary Table.

Table 7-110 DIAG_CFG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	MBIAS_HIGH_CURR_THRS[7:0]	R/W	10100010b	Threshold for Micbias High current fault diagnostics Default = ~ 27mA Nd = ((0.9×(N*16)/4095)-0⋅2)x72.83237 (mA)

7.2.35 DIAG_CFG7 Register (Address = 0x4D) [Reset = 0x48]

DIAG_CFG7 is shown in Table 7-111.

Return to the Summary Table.

Table 7-111 DIAG_CFG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	MBIAS_LOW_CURR_THRS[7:0]	R/W	01001000b	Threshold for Micbias Low current fault diagnostics Default = ~ 4mA Nd = ((0.9×(N*16)/4095)-0⋅2)x72.83237 (mA)

7.2.36 DIAG_CFG8 Register (Address = 0x4E) [Reset = 0xBA]

DIAG_CFG8 is shown in Table 7-112.

Return to the Summary Table.

Table 7-112 DIAG_CFG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	GPA_UP_THRS_FLT_THRES[7:0]	R/W	10111010b	General Purpose Analog High Threshold Default = ~ 2.6V nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V)

7.2.37 DIAG_CFG9 Register (Address = 0x4F) [Reset = 0x4B]

DIAG_CFG9 is shown in Table 7-113.

Return to the Summary Table.

Table 7-113 DIAG_CFG9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	GPA_LOW_THRS_FLT_THRES[7:0]	R/W	01001011b	General Purpose Analog Low Threshold Default = ~ 0.2V nd = ((0.9×(N*16)/4095)-0⋅225)x6 (V)

7.2.38 DIAG_CFG10 Register (Address = 0x50) [Reset = 0x88]

DIAG_CFG10 is shown in Table 7-114.

Return to the Summary Table.

Table 7-114 DIAG_CFG10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PD_MBIAS_SHRT_CKT_FLT	R/W	1b	Powerdown configuration of Micbias during Short Circuit fault 0b = No change when fault occurs 1b = Micbias is disabled when fault occurs
6	PD_MBIAS_HIGH_CURR_FLT	R/W	0b	Powerdown configuration of Micbias during High current fault 0b = No change when fault occurs 1b = Micbias is disabled when fault occurs
5	PD_MBIAS_LOW_CURR_FLT	R/W	0b	Powerdown configuration of Micbias during Low current fault 0b = No change when fault occurs 1b = Micbias is disabled when fault occurs
4	PD_MBIAS_OV_FLT	R/W	0b	Powerdown configuration of Micbias during high voltage fault 0b = No change when fault occurs 1b = Micbias is disabled when fault occurs
3	PD_MBIAS_OT_FLT	R/W	1b	Powerdown configuration of Micbias during over temperature fault 0b = No change when fault occurs 1b = Micbias is disabled when fault occurs
2	MAN_RCV_PD_FLT_CHK	R/W	0b	Manual Recovery (self clear bit) 0b = No effect 1b = Recheck fault status and re-powerup channels if they do not have any faults
1	MBIAS_FLT_AUTO_REC_EN	R/W	0b	Micbias PD on faults Auto-Recovery Enable 0d = Auto recovery from Micbias faults disabled 1d = Auto recovery enabled
0	MICBIAS_SHRT_CKT_DET_DIS	R/W	0b	Micbias Short Circuit fault detect config 0b = enable 1b = disable

7.2.39 DIAG_CFG11 Register (Address = 0x51) [Reset = 0x40]

DIAG_CFG11 is shown in Table 7-115.

Return to the Summary Table.

Table 7-115 DIAG_CFG11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	SAFEBAND_MBIAS_OV_FLT[2:0]	R/W	010b	Safeband cfgn for Mbias over voltage fault's lower boundary 0 = No safeband 1 = 30mV safeband (1LSb at 9b lvl) 2 = 60mV safeband (2LSb at 9b lvl) 3-7 = N*30mV
4-0	RESERVED	R	00000b	Reserved bits; Write only reset values

7.2.40 DIAG_CFG12 Register (Address = 0x52) [Reset = 0x44]

DIAG_CFG12 is shown in Table 7-116.

Return to the Summary Table.

Table 7-116 DIAG_CFG12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	SAFEBAND_INx_MBIAS_FLT[2:0]	R/W	010b	Safeband cfgn for INx Short to Mbias fault's upper boundary 0 = No safeband 1 = 30mV safeband (1LSb at 9b lvl) 2 = 60mV safeband (2LSb at 9b lvl) 3-7 = N*30mV
4-2	SAFEBAND_INx_OV_FLT[2:0]	R/W	001b	Safeband cfgn for INx Overvoltage fault's lower boundary 0 = No safeband 1 = 30mV safeband (1LSb at 9b lvl) 2-7 = N*30mV Dont use
1-0	RESERVED	R	00b	Reserved bits; Write only reset values

7.2.41 DIAG_CFG13 Register (Address = 0x53) [Reset = 0x00]

DIAG_CFG13 is shown in Table 7-117.

Return to the Summary Table.

Table 7-117 DIAG_CFG13 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DIAG_FORCE_EN	R/W	0b	Configuration for auto/manual enable for diag vbat, micbias, micbias load, temp 0b = Auto enabled (auto enabled if atlease one of the input channel diagnostics is enabled in DIAG_CFG0) 1b = Manual en/disable based on DIAG_CFG13 Register
6	DIAG_EN_MICBIAS_LOAD	R/W	0b	Micbias current/load channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1 0b = Diagnostic Disabled 1b = Diagnostic Enabled
5	DIAG_EN_MICBIAS	R/W	0b	Micbias channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1 0b = Diagnostic Disabled 1b = Diagnostic Enabled
4	DIAG_EN_VBAT	R/W	0b	VBAT channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1 0b = Diagnostic Disabled 1b = Diagnostic Enabled
3	DIAG_EN_TEMP_SENSE	R/W	0b	Temp sense channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1 0b = Diagnostic Disabled 1b = Diagnostic Enabled
2	DIAG_EN_AVDD	R/W	0b	AVDD channel enable for Diagnostics 0b = Diagnostic Disabled 1b = Diagnostic Enabled
1	DIAG_EN_GPA	R/W	0b	GPA channel enable for Diagnostics 0b = Diagnostic Disabled 1b = Diagnostic Enabled
0	RESERVED	R	0b	Reserved bit; Write only reset value

7.2.42 DIAG_CFG14 Register (Address = 0x54) [Reset = 0x48]

DIAG_CFG14 is shown in Table 7-118.

Return to the Summary Table.

Table 7-118 DIAG_CFG14 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0b	Reserved bit; Write only reset value
6-5	AVDD_FILT_SEL[1:0]	R/W	10b	AVDD filter select 0d = 3.5MHz 1d = 200kHz 2d = 100kHz 3d = No filter
4	RESERVED	R/W	0b	Reserved bit; Write only reset value
3-2	VBAT_FILT_SEL[1:0]	R/W	10b	VBAT filter select 0d = 3.5MHz 1d = 200kHz 2d = 100kHz 3d = No filter
1	RESERVED	R/W	0b	Reserved bit; Write only reset value
0	VBAT_SHRT_FLT	R/W	0b	Cfgn on INx short to VBAT 0 = INx Overvoltage and INx short to VBAT are separate 1 = INx Overvoltage and INx short to VBAT are Ord together as VBAT short fault

7.2.43 DIAG_MON_MSB_VBAT Register (Address = 0x56) [Reset = 0x00]

DIAG_MON_MSB_VBAT is shown in Table 7-119.

Return to the Summary Table.

Table 7-119 DIAG_MON_MSB_VBAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_VBAT[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.44 DIAG_MON_LSB_VBAT Register (Address = 0x57) [Reset = 0x00]

DIAG_MON_LSB_VBAT is shown in Table 7-120.

Return to the Summary Table.

Table 7-120 DIAG_MON_LSB_VBAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_VBAT[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	0000b	Channel ID

7.2.45 DIAG_MON_MSB_MBIAS Register (Address = 0x58) [Reset = 0x00]

DIAG_MON_MSB_MBIAS is shown in Table 7-121.

Return to the Summary Table.

Table 7-121 DIAG_MON_MSB_MBIAS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_MBIAS[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.46 DIAG_MON_LSB_MBIAS Register (Address = 0x59) [Reset = 0x01]

DIAG_MON_LSB_MBIAS is shown in Table 7-122.

Return to the Summary Table.

Table 7-122 DIAG_MON_LSB_MBIAS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_MBIAS[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	0001b	Channel ID

7.2.47 DIAG_MON_MSB_IN1P Register (Address = 0x5A) [Reset = 0x00]

DIAG_MON_MSB_IN1P is shown in Table 7-123.

Return to the Summary Table.

Table 7-123 DIAG_MON_MSB_IN1P Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_IN_CH1P[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.48 DIAG_MON_LSB_IN1P Register (Address = 0x5B) [Reset = 0x02]

DIAG_MON_LSB_IN1P is shown in Table 7-124.

Return to the Summary Table.

Table 7-124 DIAG_MON_LSB_IN1P Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_IN_CH1P[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	0010b	Channel ID

7.2.49 DIAG_MON_MSB_IN1M Register (Address = 0x5C) [Reset = 0x00]

DIAG_MON_MSB_IN1M is shown in Table 7-125.

Return to the Summary Table.

Table 7-125 DIAG_MON_MSB_IN1M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_IN_CH1N[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.50 DIAG_MON_LSB_IN1M Register (Address = 0x5D) [Reset = 0x03]

DIAG_MON_LSB_IN1M is shown in Table 7-126.

Return to the Summary Table.

Table 7-126 DIAG_MON_LSB_IN1M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_IN_CH1N[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	0011b	Channel ID

7.2.51 DIAG_MON_MSB_IN2P Register (Address = 0x5E) [Reset = 0x00]

DIAG_MON_MSB_IN2P is shown in Table 7-127.

Return to the Summary Table.

Table 7-127 DIAG_MON_MSB_IN2P Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_IN_CH2P[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.52 DIAG_MON_LSB_IN2P Register (Address = 0x5F) [Reset = 0x04]

DIAG_MON_LSB_IN2P is shown in Table 7-128.

Return to the Summary Table.

Table 7-128 DIAG_MON_LSB_IN2P Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_IN_CH2P[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	0100b	Channel ID

7.2.53 DIAG_MON_MSB_IN2M Register (Address = 0x60) [Reset = 0x00]

DIAG_MON_MSB_IN2M is shown in Table 7-129.

Return to the Summary Table.

Table 7-129 DIAG_MON_MSB_IN2M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_IN_CH2N[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.54 DIAG_MON_LSB_IN2M Register (Address = 0x61) [Reset = 0x05]

DIAG_MON_LSB_IN2M is shown in Table 7-130.

Return to the Summary Table.

Table 7-130 DIAG_MON_LSB_IN2M Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_IN_CH2N[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	0101b	Channel ID

7.2.55 DIAG_MON_MSB_TEMP Register (Address = 0x6A) [Reset = 0x00]

DIAG_MON_MSB_TEMP is shown in Table 7-131.

Return to the Summary Table.

Table 7-131 DIAG_MON_MSB_TEMP Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_TEMP[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.56 DIAG_MON_LSB_TEMP Register (Address = 0x6B) [Reset = 0x0A]

DIAG_MON_LSB_TEMP is shown in Table 7-132.

Return to the Summary Table.

Table 7-132 DIAG_MON_LSB_TEMP Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_TEMP[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	1010b	Channel ID

7.2.57 DIAG_MON_MSB_MBIAS_LOAD Register (Address = 0x6C) [Reset = 0x00]

DIAG_MON_MSB_MBIAS_LOAD is shown in Table 7-133.

Return to the Summary Table.

Table 7-133 DIAG_MON_MSB_MBIAS_LOAD Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_MBIAS_LOAD[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.58 DIAG_MON_LSB_MBIAS_LOAD Register (Address = 0x6D) [Reset = 0x0B]

DIAG_MON_LSB_MBIAS_LOAD is shown in Table 7-134.

Return to the Summary Table.

Table 7-134 DIAG_MON_LSB_MBIAS_LOAD Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_MBIAS_LOAD[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	1011b	Channel ID

7.2.59 DIAG_MON_MSB_AVDD Register (Address = 0x6E) [Reset = 0x00]

DIAG_MON_MSB_AVDD is shown in Table 7-135.

Return to the Summary Table.

Table 7-135 DIAG_MON_MSB_AVDD Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_AVDD[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.60 DIAG_MON_LSB_AVDD Register (Address = 0x6F) [Reset = 0x0C]

DIAG_MON_LSB_AVDD is shown in Table 7-136.

Return to the Summary Table.

Table 7-136 DIAG_MON_LSB_AVDD Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_AVDD[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	1100b	Channel ID

7.2.61 DIAG_MON_MSB_GPA Register (Address = 0x70) [Reset = 0x00]

DIAG_MON_MSB_GPA is shown in Table 7-137.

Return to the Summary Table.

Table 7-137 DIAG_MON_MSB_GPA Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIAG_MON_MSB_GPA[7:0]	R	00000000b	Diagnostic SAR Monitor Data MSB Byte

7.2.62 DIAG_MON_LSB_GPA Register (Address = 0x71) [Reset = 0x0D]

DIAG_MON_LSB_GPA is shown in Table 7-138.

Return to the Summary Table.

Table 7-138 DIAG_MON_LSB_GPA Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DIAG_MON_LSB_GPA[3:0]	R	0000b	Diagnostic SAR Monitor Data LSB Nibble
3-0	Channel[3:0]	R	1101b	Channel ID

7.2.63 BOOST_CFG Register (Address = 0x72) [Reset = 0x00]

BOOST_CFG is shown in Table 7-139.

Return to the Summary Table.

Table 7-139 BOOST_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BOOST_DIS	R/W	0b	Boost Enable/Disable 0d = Internal Boost enable 1d = Internal Boost disable/bypass
6	BOOST_OCPEN	R/W	0b	Boost Over Current Protection Enable/Disable 0d = Boost OCP is enable 1d = Boost OCP is disable
5	BOOST_PDz_FLT	R/W	0b	Boost PD cfgn 0d = Boost is powered down if Micbias is powered down due to faults 1d = Boost is NOT powered down if Micbias is powered down due to faults
4	RESERVED	R/W	0b	Reserved bit; Write only reset value
3	RESERVED	R/W	0b	Reserved bit; Write only reset value
2-0	RESERVED	R	000b	Reserved bits; Write only reset values

7.2.64 MICBIAS_CFG Register (Address = 0x73) [Reset = 0xA0]

MICBIAS_CFG is shown in Table 7-140.

Return to the Summary Table.

Table 7-140 MICBIAS_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	MBIAS_VAL[3:0]	R/W	1010b	MicBias Value 0d = Microphone Bias output is bypassed to BSTOUT/HVDD 1d = Microphone Bias is set to 3.0 V 2d = Microphone Bias is set to 3.5 V 3d = Microphone Bias is set to 4.0 V 4d = Microphone Bias is set to 4.5 V 5d = Microphone Bias is set to 5 V 6d = Microphone Bias is set to 5.5 V 7d = Microphone Bias is set to 6 V 8d = Microphone Bias is set to 6.5 V 9d = Microphone Bias is set to 7 V 10d = Microphone Bias is set to 7.5 V 11d = Microphone Bias is set to 8 V 12d = Microphone Bias is set to 8.5 V 13d = Microphone Bias is set to 9 V 14d = Microphone Bias is set to 9.5 V 15d = Microphone Bias is set to 10 V
3-0	RESERVED	R	0000b	Reserved bits; Write only reset value