JAJSNP9 January   2024 TAA5412-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements: I2C Interface
    8. 5.8  Switching Characteristics: I2C Interface
    9. 5.9  Timing Requirements: TDM, I2S or LJ Interface
    10. 5.10 Switching Characteristics: TDM, I2S or LJ Interface
    11. 5.11 Timing Requirements: PDM Digital Microphone Interface
    12. 5.12 Switching Characteristics: PDM Digial Microphone Interface
    13. 5.13 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
      2. 6.3.2 Using Multiple Devices With Shared Buses
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Input Channel Configuration
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Input DC Fault Diagnostics
        1. 6.3.7.1 Fault Conditions
          1. 6.3.7.1.1 Input Pin Short to Ground
          2. 6.3.7.1.2 Input Pin Short to MICBIAS
          3. 6.3.7.1.3 Open Inputs
          4. 6.3.7.1.4 Short Between INxP and INxM
          5. 6.3.7.1.5 Input Pin Overvoltage
          6. 6.3.7.1.6 Input Pin Short to VBAT_IN
        2. 6.3.7.2 Fault Reporting
          1. 6.3.7.2.1 Overcurrent and Overtemperature Protection
      8. 6.3.8 Signal-Chain Processing
        1. 6.3.8.1 ADC Signal-Chain
          1. 6.3.8.1.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.8.1.2 Programmable Channel Gain Calibration
          3. 6.3.8.1.3 Programmable Channel Phase Calibration
          4. 6.3.8.1.4 Programmable Digital High-Pass Filter
          5. 6.3.8.1.5 Programmable Digital Biquad Filters
          6. 6.3.8.1.6 Programmable Channel Summer and Digital Mixer
          7. 6.3.8.1.7 Configurable Digital Decimation Filters
            1. 6.3.8.1.7.1 Linear Phase Filters
              1. 6.3.8.1.7.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 6.3.8.1.7.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 6.3.8.1.7.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 6.3.8.1.7.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 6.3.8.1.7.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 6.3.8.1.7.1.6 Sampling Rate: 384kHz or 352.8kHz
      9. 6.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 6.4 Device Functional Modes
  8. 7 Register Maps
    1. 7.1 TAA5412-Q1 Registers
    2. 7.2 TAA5412-Q1 Registers
    3. 7.3 TAA5412-Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1 Overview

The TAA5412-Q1 is from a scalable TAC5xxx-Q1 family of devices. As with the extended family of devices, the TAA5412-Q1 consists of a high-performance, low-power, flexible, multichannel, audio analog-to-digital converter (ADC) and digital-to-analog converter (DAC) with extensive feature integration. This device is intended for automotive applications such as vehicle cabin active noise cancellation, hands-free in-vehicle communication, emergency call, and multimedia applications. The high dynamic range of this device enables far-field audio recording with high fidelity. This device integrates a host of features that reduce cost, board space, and power consumption in space-constrained automotive sub-system designs. Package, performance, and device-compatible configuration registers make this device well suited for scalable system designs.

The TAA5412-Q1 consists of the following blocks:

  • 2-channel, multibit, high-performance delta-sigma (ΔΣ) ADCs
  • Configurable single-ended or differential audio inputs with high voltage signal swing
  • High-voltage, low-noise programmable microphone bias output
  • Highly flexible, comprehensive input fault diagnostic
  • Automatic gain controller (AGC)
  • Programmable decimation filters with linear-phase or low-latency filter
  • Programmable channel gain, volume control, and biquad filters for each channel
  • Programmable phase and gain calibration with fine resolution for each channel
  • Programmable high-pass filter (HPF) and digital channel mixer
  • Pulse density modulation (PDM) digital microphone interface with high-performance decimation filter
  • Integrated low-jitter, phase-locked loop (PLL) supporting a wide range of system clocks
  • Integrated digital and analog voltage regulators to support single-supply operation

Communication to the TAA5412-Q1 for configuring the control registers is supported using an I2C or SPI interface. The device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I2S, or left-justified (LJ)] to transmit audio data seamlessly in the system across devices.

The device can support multiple devices by sharing the common I2C and TDM buses across devices. Moreover, the device includes a daisy-chain feature and a secondary audio serial output data pin. These features relax the shared TDM bus timing requirements and board design complexities when operating multiple devices for applications requiring high audio data bandwidth.

Abbreviations for Register References lists the reference abbreviations used throughout this document to registers that control the device.

Table 6-1 Abbreviations for Register References
REFERENCEABBREVIATIONDESCRIPTIONEXAMPLE
Page y, register z, bit kPy_Rz_DkSingle data bit. The value of a single bit in a register.Page 4, register 36, bit 0 = P4_R36_D0
Page y, register z, bits k-mPy_Rz_D[k:m]Range of data bits. A range of data bits (inclusive).Page 4, register 36, bits 3, 2, 1, 0 = P4_R36_D[3:0]
Page y, register zPy_RzOne entire register. All eight bits in the register as a unit.Page 4, register 36 = P4_R36
Page y, registers z-nPy_Rz-RnRange of registers. A range of registers in the same page.Page 4, registers 36, 37, 38 = P4_R36-R38