JAJSNP9 January   2024 TAA5412-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements: I2C Interface
    8. 5.8  Switching Characteristics: I2C Interface
    9. 5.9  Timing Requirements: TDM, I2S or LJ Interface
    10. 5.10 Switching Characteristics: TDM, I2S or LJ Interface
    11. 5.11 Timing Requirements: PDM Digital Microphone Interface
    12. 5.12 Switching Characteristics: PDM Digial Microphone Interface
    13. 5.13 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
      2. 6.3.2 Using Multiple Devices With Shared Buses
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Input Channel Configuration
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Input DC Fault Diagnostics
        1. 6.3.7.1 Fault Conditions
          1. 6.3.7.1.1 Input Pin Short to Ground
          2. 6.3.7.1.2 Input Pin Short to MICBIAS
          3. 6.3.7.1.3 Open Inputs
          4. 6.3.7.1.4 Short Between INxP and INxM
          5. 6.3.7.1.5 Input Pin Overvoltage
          6. 6.3.7.1.6 Input Pin Short to VBAT_IN
        2. 6.3.7.2 Fault Reporting
          1. 6.3.7.2.1 Overcurrent and Overtemperature Protection
      8. 6.3.8 Signal-Chain Processing
        1. 6.3.8.1 ADC Signal-Chain
          1. 6.3.8.1.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.8.1.2 Programmable Channel Gain Calibration
          3. 6.3.8.1.3 Programmable Channel Phase Calibration
          4. 6.3.8.1.4 Programmable Digital High-Pass Filter
          5. 6.3.8.1.5 Programmable Digital Biquad Filters
          6. 6.3.8.1.6 Programmable Channel Summer and Digital Mixer
          7. 6.3.8.1.7 Configurable Digital Decimation Filters
            1. 6.3.8.1.7.1 Linear Phase Filters
              1. 6.3.8.1.7.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 6.3.8.1.7.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 6.3.8.1.7.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 6.3.8.1.7.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 6.3.8.1.7.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 6.3.8.1.7.1.6 Sampling Rate: 384kHz or 352.8kHz
      9. 6.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 6.4 Device Functional Modes
  8. 7 Register Maps
    1. 7.1 TAA5412-Q1 Registers
    2. 7.2 TAA5412-Q1 Registers
    3. 7.3 TAA5412-Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 TAA5412-Q1 Registers

Table 7-1 lists the memory-mapped registers for the TAA5412-Q1 registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 TAA5412-Q1 Registers
AddressAcronymRegister NameReset ValueSection
0x0PAGE_CFGDevice page register0x00PAGE_CFG Register (Address = 0x0) [Reset = 0x00]
0x1SW_RESETSoftware reset register0x00SW_RESET Register (Address = 0x1) [Reset = 0x00]
0x2VREF_CFG0x00VREF_CFG Register (Address = 0x2) [Reset = 0x00]
0x3AVDD_IOVDD_STS0x00AVDD_IOVDD_STS Register (Address = 0x3) [Reset = 0x00]
0x4MISC_CFG0x00MISC_CFG Register (Address = 0x4) [Reset = 0x00]
0x5MISC_CFG10x15MISC_CFG1 Register (Address = 0x5) [Reset = 0x15]
0x7MISC_CFG0Misc. configuration register0x00MISC_CFG0 Register (Address = 0x7) [Reset = 0x00]
0xAGPIO1_CFG0GPIO1 configuration register 00x32GPIO1_CFG0 Register (Address = 0xA) [Reset = 0x32]
0xCGPO1A_CFG0GPO1A configuration register 00x00GPO1A_CFG0 Register (Address = 0xC) [Reset = 0x00]
0xDGPI_CFGGPI1 configuration register 00x00GPI_CFG Register (Address = 0xD) [Reset = 0x00]
0xEGPO_GPI_VALGPIO, GPO output value register0x00GPO_GPI_VAL Register (Address = 0xE) [Reset = 0x00]
0xFINTF_CFG0Interface configuration register 00x00INTF_CFG0 Register (Address = 0xF) [Reset = 0x00]
0x10INTF_CFG1Interface configuration register 10x52INTF_CFG1 Register (Address = 0x10) [Reset = 0x52]
0x11INTF_CFG2Interface configuration register 20x80INTF_CFG2 Register (Address = 0x11) [Reset = 0x80]
0x12INTF_CFG3Interface configuration register 30x00INTF_CFG3 Register (Address = 0x12) [Reset = 0x00]
0x13INTF_CFG4Interface configuration register 30x00INTF_CFG4 Register (Address = 0x13) [Reset = 0x00]
0x14INTF_CFG5Interface configuration register 40x00INTF_CFG5 Register (Address = 0x14) [Reset = 0x00]
0x15INTF_CFG6Interface configuration register 50x00INTF_CFG6 Register (Address = 0x15) [Reset = 0x00]
0x18ASI_CFG0ASI configuration register 00x40ASI_CFG0 Register (Address = 0x18) [Reset = 0x40]
0x19ASI_CFG1ASI configuration register 10x00ASI_CFG1 Register (Address = 0x19) [Reset = 0x00]
0x1APASI_CFG0Primary ASI configuration register 00x30PASI_CFG0 Register (Address = 0x1A) [Reset = 0x30]
0x1BPASI_TX_CFG0PASI TX configuration register 00x00PASI_TX_CFG0 Register (Address = 0x1B) [Reset = 0x00]
0x1CPASI_TX_CFG1PASI TX configuration register 10x00PASI_TX_CFG1 Register (Address = 0x1C) [Reset = 0x00]
0x1DPASI_TX_CFG2PASI TX configuration register 20x00PASI_TX_CFG2 Register (Address = 0x1D) [Reset = 0x00]
0x1EPASI_TX_CH1_CFGPASI TX Channel 1 configuration register0x20PASI_TX_CH1_CFG Register (Address = 0x1E) [Reset = 0x20]
0x1FPASI_TX_CH2_CFGPASI TX Channel 2 configuration register0x21PASI_TX_CH2_CFG Register (Address = 0x1F) [Reset = 0x21]
0x20PASI_TX_CH3_CFGPASI TX Channel 3 configuration register0x02PASI_TX_CH3_CFG Register (Address = 0x20) [Reset = 0x02]
0x21PASI_TX_CH4_CFGPASI TX Channel 4 configuration register0x03PASI_TX_CH4_CFG Register (Address = 0x21) [Reset = 0x03]
0x22PASI_TX_CH5_CFGPASI TX Channel 5 configuration register0x04PASI_TX_CH5_CFG Register (Address = 0x22) [Reset = 0x04]
0x23PASI_TX_CH6_CFGPASI TX Channel 6 configuration register0x05PASI_TX_CH6_CFG Register (Address = 0x23) [Reset = 0x05]
0x24PASI_TX_CH7_CFGPASI TX Channel 7 configuration register0x06PASI_TX_CH7_CFG Register (Address = 0x24) [Reset = 0x06]
0x26PASI_RX_CFG0PASI RX configuration register 00x00PASI_RX_CFG0 Register (Address = 0x26) [Reset = 0x00]
0x32CLK_CFG0Clock configuration register 00x00CLK_CFG0 Register (Address = 0x32) [Reset = 0x00]
0x33CLK_CFG1Clock configuration register 10x00CLK_CFG1 Register (Address = 0x33) [Reset = 0x00]
0x34CLK_CFG2Clock configuration register 20x40CLK_CFG2 Register (Address = 0x34) [Reset = 0x40]
0x35CNT_CLK_CFG0controller mode clock configuration register 00x00CNT_CLK_CFG0 Register (Address = 0x35) [Reset = 0x00]
0x36CNT_CLK_CFG1controller mode clock configuration register 10x00CNT_CLK_CFG1 Register (Address = 0x36) [Reset = 0x00]
0x37CNT_CLK_CFG2controller mode clock configuration register 20x20CNT_CLK_CFG2 Register (Address = 0x37) [Reset = 0x20]
0x38CNT_CLK_CFG3controller mode clock configuration register 30x00CNT_CLK_CFG3 Register (Address = 0x38) [Reset = 0x00]
0x39CNT_CLK_CFG4controller mode clock configuration register 40x00CNT_CLK_CFG4 Register (Address = 0x39) [Reset = 0x00]
0x3ACNT_CLK_CFG5controller mode clock configuration register 50x00CNT_CLK_CFG5 Register (Address = 0x3A) [Reset = 0x00]
0x3BCNT_CLK_CFG6controller mode clock configuration register 60x00CNT_CLK_CFG6 Register (Address = 0x3B) [Reset = 0x00]
0x3CCLK_ERR_STS0Clock error and status register 00x00CLK_ERR_STS0 Register (Address = 0x3C) [Reset = 0x00]
0x3DCLK_ERR_STS1Clock error and status register 10x00CLK_ERR_STS1 Register (Address = 0x3D) [Reset = 0x00]
0x3ECLK_DET_STS0Clock ratio detection register 00x00CLK_DET_STS0 Register (Address = 0x3E) [Reset = 0x00]
0x3FCLK_DET_STS1Clock ratio detection register 10x00CLK_DET_STS1 Register (Address = 0x3F) [Reset = 0x00]
0x40CLK_DET_STS2Clock ratio detection register 20x00CLK_DET_STS2 Register (Address = 0x40) [Reset = 0x00]
0x41CLK_DET_STS3Clock ratio detection register 30x00CLK_DET_STS3 Register (Address = 0x41) [Reset = 0x00]
0x42INT_CFGInterrupt configuration register0x00INT_CFG Register (Address = 0x42) [Reset = 0x00]
0x4BADC_DAC_MISC_CFGADC overload Response configuration register0x00ADC_DAC_MISC_CFG Register (Address = 0x4B) [Reset = 0x00]
0x4EPWR_TUNE_CFG0Power tune configuration register 00x00PWR_TUNE_CFG0 Register (Address = 0x4E) [Reset = 0x00]
0x50ADC_CH1_CFG0ADC Channel 1 configuration register 00x00ADC_CH1_CFG0 Register (Address = 0x50) [Reset = 0x00]
0x52ADC_CH1_CFG2ADC Channel 1 configuration register 20xA1ADC_CH1_CFG2 Register (Address = 0x52) [Reset = 0xA1]
0x53ADC_CH1_CFG3ADC Channel 1 configuration register 30x80ADC_CH1_CFG3 Register (Address = 0x53) [Reset = 0x80]
0x54ADC_CH1_CFG4ADC Channel 1 configuration register 40x00ADC_CH1_CFG4 Register (Address = 0x54) [Reset = 0x00]
0x55ADC_CH2_CFG0ADC Channel 2 configuration register 00x00ADC_CH2_CFG0 Register (Address = 0x55) [Reset = 0x00]
0x57ADC_CH2_CFG2Channel 2 configuration register 20xA1ADC_CH2_CFG2 Register (Address = 0x57) [Reset = 0xA1]
0x58ADC_CH2_CFG3ADC Channel 2 configuration register 30x80ADC_CH2_CFG3 Register (Address = 0x58) [Reset = 0x80]
0x59ADC_CH2_CFG4ADC Channel 2 configuration register 40x00ADC_CH2_CFG4 Register (Address = 0x59) [Reset = 0x00]
0x5AADC_CH3_CFG0ADC Channel 3 configuration register 00x00ADC_CH3_CFG0 Register (Address = 0x5A) [Reset = 0x00]
0x5BADC_CH3_CFG2ADC Channel 3 configuration register 20xA1ADC_CH3_CFG2 Register (Address = 0x5B) [Reset = 0xA1]
0x5CADC_CH3_CFG3ADC Channel 3 configuration register 30x80ADC_CH3_CFG3 Register (Address = 0x5C) [Reset = 0x80]
0x5DADC_CH3_CFG4ADC Channel 3 configuration register 40x00ADC_CH3_CFG4 Register (Address = 0x5D) [Reset = 0x00]
0x5EADC_CH4_CFG0ADC Channel 4 configuration register 00x00ADC_CH4_CFG0 Register (Address = 0x5E) [Reset = 0x00]
0x5FADC_CH4_CFG2Channel 4 configuration register 20xA1ADC_CH4_CFG2 Register (Address = 0x5F) [Reset = 0xA1]
0x60ADC_CH4_CFG3ADC Channel 4 configuration register 30x80ADC_CH4_CFG3 Register (Address = 0x60) [Reset = 0x80]
0x61ADC_CH4_CFG4ADC Channel 4 configuration register 40x00ADC_CH4_CFG4 Register (Address = 0x61) [Reset = 0x00]
0x72DSP_CFG0DSP configuration register 00x18DSP_CFG0 Register (Address = 0x72) [Reset = 0x18]
0x76CH_ENChannel enable configuration register0xCCCH_EN Register (Address = 0x76) [Reset = 0xCC]
0x77DYN_PUPD_CFGPower up configuration register0x00DYN_PUPD_CFG Register (Address = 0x77) [Reset = 0x00]
0x78PWR_CFGPower up configuration register0x00PWR_CFG Register (Address = 0x78) [Reset = 0x00]
0x79DEV_STS0Device status value register 00x00DEV_STS0 Register (Address = 0x79) [Reset = 0x00]
0x7ADEV_STS1Device status value register 10x80DEV_STS1 Register (Address = 0x7A) [Reset = 0x80]
0x7EI2C_CKSUMI2C checksum register0x00I2C_CKSUM Register (Address = 0x7E) [Reset = 0x00]

7.1.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 7-2.

Return to the Summary Table.

The device memory map is divided into pages. This register sets the page.

Table 7-2 PAGE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W00000000bThese bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255

7.1.2 SW_RESET Register (Address = 0x1) [Reset = 0x00]

SW_RESET is shown in Table 7-3.

Return to the Summary Table.

This register is the software reset register. Asserting a software reset places all register values in their default power-on-reset (POR) state.

Table 7-3 SW_RESET Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0000000bReserved bits; Write only reset value
0SW_RESETR/W0bSoftware reset. This bit is self clearing.
0d = Do not reset
1d = Reset all registers to their reset values

7.1.3 VREF_CFG Register (Address = 0x2) [Reset = 0x00]

VREF_CFG is shown in Table 7-4.

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Table 7-4 VREF_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W00bReserved bits; Write only reset values
5-4VREF_QCHG[1:0]R/W00bThe duration of the quick-charge for the VREF external capacitor is set using an internal series impedance of 200 Ω.
0d = VREF quick-charge duration of 3.5 ms (typical)
1d = VREF quick-charge duration of 10 ms (typical)
2d = VREF quick-charge duration of 50 ms (typical)
3d = VREF quick-charge duration of 100 ms (typical)
3SLEEP_EXIT_VREF_ENR/W0bSleep mode exit configuration
0d = Only DREG Enabled
1d = DREG and VREF enabled
2AVDD_MODER/W0bAVDD mode configuration.
0d = Internal AREG regulator is used (Should be used for AVDD > 2V)
1d = AVDD 1.8V used directly for AREG (Strictly use this setting for AVDD 1.7V-1.9V)
1IOVDD_IO_MODER/W0bIOVDD mode configuration.
0d = IOVDD at 3.3V / 1.8V / 1.2V (speed limitation applicable for 1.8V and 1.2V)
1d = IOVDD at 1.8V / 1.2V only (no speed limitation - Strictly don't use this setting for IOVDD > 2V).
0SLEEP_ENZR/W0bSleep mode setting.
0d = Device is in sleep mode
1d = Device is not in sleep mode

7.1.4 AVDD_IOVDD_STS Register (Address = 0x3) [Reset = 0x00]

AVDD_IOVDD_STS is shown in Table 7-5.

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Table 7-5 AVDD_IOVDD_STS Register Field Descriptions
BitFieldTypeResetDescription
7AVDD_MODE_STSR0bAVDD mode status flag register.
0d = AVDD_MODE as per configured
1d = AVDD > 2V (AVDD_MODE forced to 0d)
6IOVDD_IO_MODE_STSR0bIOVDD mode status flag register.
0d = IOVDD_MODE as per configured
1d = IOVDD > 2V (IOVDD_IO_MODE forced to 0d)
5-2RESERVEDR0000bReserved bits; Write only reset values
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR/W0bReserved bit; Write only reset value

7.1.5 MISC_CFG Register (Address = 0x4) [Reset = 0x00]

MISC_CFG is shown in Table 7-6.

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Table 7-6 MISC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6IGNORE_CLK_ERRR/W0bClock error detection action
0b = Reset on Clock error
1b = Ignore Clock error
5RESERVEDR/W0bReserved bit; Write only reset value
4RESERVEDR/W0bReserved bit; Write only reset value
3RESERVEDR/W0bReserved bit; Write only reset value
2RESERVEDR/W0bReserved bit; Write only reset value
1I2C_BRDCAST_ENR/W0b I2C broadcast addressing setting.
0d = I2C broadcast mode disabled
1d = I2C broadcast mode enabled; the I2C target address is fixed with pin-controlled LSB bits as '0'
0RESERVEDR/W0bReserved bit; Write only reset value

7.1.6 MISC_CFG1 Register (Address = 0x5) [Reset = 0x15]

MISC_CFG1 is shown in Table 7-7.

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Table 7-7 MISC_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6INCAP_QCHG[1:0]R/W00bThe duration of the quick-charge for the external AC-coupling capacitor is set using an internal series impedance of 800 Ω.
0d = INxP, INxM quick-charge duration of 2.5 ms (typical)
1d = INxP, INxM quick-charge duration of 12.5 ms (typical)
2d = INxP, INxM quick-charge duration of 25 ms (typical)
3d = INxP, INxM quick-charge duration of 50 ms (typical)
5-4SHDN_CFG[1:0]R/W01bShutdown configuration.
0d = DREG is powered down immediately after IOVDD is deasserted
1d = DREG remains active to enable a clean shut down until a time-out(DREG_KA_TIME) is reached; after the time-out period, DREG is forced to power off
2d = DREG remains active until the device cleanly shuts down
3d = Reserved; Don't use
3-2DREG_KA_TIME[1:0]R/W01bThese bits set how long DREG remains active after IOVDD is deasserted.
0d = DREG remains active for 30 ms (typical)
1d = DREG remains active for 25 ms (typical)
2d = DREG remains active for 10 ms (typical)
3d = DREG remains active for 5 ms (typical)
1-0RESERVEDR/W01bReserved bits; Write only reset values

7.1.7 MISC_CFG0 Register (Address = 0x7) [Reset = 0x00]

MISC_CFG0 is shown in Table 7-8.

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This register configures the device Misc.

Table 7-8 MISC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6RESERVEDR/W0bReserved bit; Write only reset value
5RESERVEDR/W0bReserved bit; Write only reset value
4HW_RESET_ON_CLK_STOP_ENR/W0bAssertion of Hard Reset when clock selected by CLK_SRC_SEL is not available for 2ms config
0d = disable
1d = enable
3-0RESERVEDR0000bReserved bits; Write only reset values

7.1.8 GPIO1_CFG0 Register (Address = 0xA) [Reset = 0x32]

GPIO1_CFG0 is shown in Table 7-9.

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This register is the GPIO1 configuration register 0.

Table 7-9 GPIO1_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-4GPIO1_CFG[3:0]R/W0011bGPIO1 configuration.
0d = GPIO1 is disabled
1d = GPIO1 is configured as a general-purpose input (GPI) or any other input function
2d = GPIO1 is configured as a general-purpose output (GPO)
3d = GPIO1 is configured as a chip interrupt output (IRQ)
4d = GPIO1 is configured as a PDM clock output (PDMCLK)
5d = GPIO1 is configured as primary ASI DOUT
6d = GPIO1 is configured as primary ASI DOUT2
7d = GPIO1 is configured as secondary ASI DOUT
8d = GPIO1 is configured as secondary ASI DOUT2
9d = GPIO1 is configured as secondary ASI BCLK output
10d = GPIO1 is configured as secondary ASI FSYNC output
11d = GPIO1 is configured as general purpose CLKOUT
12d = GPIO1 is configured as PASI DOUT and SASI DOUT muxed
13d = GPIO1 is configured as DAISY_OUT for DIN Daisy
14d to 15d = Reserved
3RESERVEDR0bReserved bit; Write only reset value
2-0GPIO1_DRV[2:0]R/W010bGPIO1 output drive configuration. (Not valid if GPIO1_CFG configured as I2S out)
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved; Don't use

7.1.9 GPO1A_CFG0 Register (Address = 0xC) [Reset = 0x00]

GPO1A_CFG0 is shown in Table 7-10.

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This register is the GPO1 configuration register 0.

Table 7-10 GPO1A_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-4GPO1A_CFG[3:0]R/W0000bGPO1A configuration.(Max frequency is limited to 6MHz. For SPI mode, this pin act as POCI and the below configuration settings are not applicable) (Buskeeper en is not supported when used as DOUT)
0d = GPO1A is disabled
1d = GPO1A is configured as a general-purpose input (GPI) or any other input function
2d = GPO1A is configured as a general-purpose output (GPO)
3d = GPO1A is configured as a chip interrupt output (IRQ)
4d = GPO1A is configured as a PDM clock output (PDMCLK)
5d = GPO1A is configured as primary ASI DOUT
6d = GPO1A is configured as primary ASI DOUT2
7d = GPO1A is configured as secondary ASI DOUT
8d = GPO1A is configured as secondary ASI DOUT2
9d = GPO1A is configured as secondary ASI BCLK output
10d = GPO1A is configured as secondary ASI FSYNC output
11d = GPO1A is configured as general purpose CLKOUT
12d = GPO1A is configured as PASI DOUT and SASI DOUT muxed
13d = GPO1A is configured as DAISY_OUT for DIN Daisy
14d to 15d = Reserved
3SPI_POCI_CFGR/W0bSPI POCI configuration.
0d = GPO1A pin act as SPI POCI output (max frequency limited to 6MHz) and GPO1A_CFG and GPO1A_DRV settings are ignored.
0d = GPIO1A pin act as SPI POCI output for high speed use case and GPIO1A_CFG and GPIO1A_DRV settings are ignored.
2-0GPO1A_DRV[2:0]R/W000bGPO1A output drive configuration. (Not valid if GPO1A_CFG configured as I2S out) (This is GPO1A in Auto-device but max frequency is limited to 6MHz. For SPI mode, this pin act as SSZ and the below configuration settings are not applicable)
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved; Don't use

7.1.10 GPI_CFG Register (Address = 0xD) [Reset = 0x00]

GPI_CFG is shown in Table 7-11.

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This register is the GPI1 configuration register 0.

Table 7-11 GPI_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR000000bReserved bits; Write only reset values
1GPI1A_CFGR/W0bGPI1A configuration.
0d = GPI1A is disabled
1d = GPI1A is configured as a general-purpose input (GPI) or any other input function
0GPI2A_CFGR/W0bGPI2A configuration.
0d = GPI2A is disabled
1d = GPI2A is configured as a general-purpose input (GPI) or any other input function

7.1.11 GPO_GPI_VAL Register (Address = 0xE) [Reset = 0x00]

GPO_GPI_VAL is shown in Table 7-12.

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This register is the GPIO and GPO output value register.

Table 7-12 GPO_GPI_VAL Register Field Descriptions
BitFieldTypeResetDescription
7GPIO1_VALR/W0bGPIO1 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
6RESERVEDR/W0bReserved bit; Write only reset value
5GPO1A_VALR/W0bGPO1A output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
4RESERVEDR0bReserved bit; Write only reset value
3GPIO1_MONR0bGPIO1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
2GPI2A_MONR0bGPI2A monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
1GPI1A_MONR0bGPI1A monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
0RESERVEDR0bReserved bit; Write only reset value

7.1.12 INTF_CFG0 Register (Address = 0xF) [Reset = 0x00]

INTF_CFG0 is shown in Table 7-13.

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This register is the interface configuration register 0.

Table 7-13 INTF_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5CCLK_SEL[1:0]R/W00bCCLK select configuration.
0d = cclk is disabled
1d = GPIO1
2d = GPI2A
3d = GPI1A
4-2PASI_DIN2_SEL[2:0]R/W000bPrimary ASI DIN2 select configuration.
0d = Primary ASI DIN2 is disabled
1d = GPIO1
2d = GPI2A
3d = GPI1A
4d = DOUT
5d = Primary ASI DIN
6d to 7d = Reserved
1PASI_BCLK_SELR/W0bPrimary ASI BCLK select configuration.
0d = Primary ASI BCLK is BCLK
1d = Primary ASI BCLK is Secondary ASI BCLK
0PASI_FSYNC_SELR/W0bPrimary ASI FSYNC select configuration.
0d = Primary ASI FSYNC is FSYNC
1d = Primary ASI FSYNC is Secondary ASI FSYNC

7.1.13 INTF_CFG1 Register (Address = 0x10) [Reset = 0x52]

INTF_CFG1 is shown in Table 7-14.

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This register is the interface configuration register 1.

Table 7-14 INTF_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-4DOUT_SEL[3:0]R/W0101bDOUT select configuration.
0d = DOUT is disabled
1d = DOUT is configured as input
2d = DOUT is configured as a general-purpose output (GPO)
3d = DOUT is configured as a chip interrupt output (IRQ)
4d = DOUT is configured as a PDM clock output (PDMCLK)
5d = DOUT is configured as primary ASI DOUT
6d = DOUT is configured as primary ASI DOUT2
7d = DOUT is configured as secondary ASI DOUT
8d = DOUT is configured as secondary ASI DOUT2
9d = DOUT is configured as secondary ASI BCLK output
10d = DOUT is configured as secondary ASI FSYNC output
11d = DOUT is configured as general purpose CLKOUT
12d = DOUT is configured as PASI DOUT and SASI DOUT muxed
13d = DOUT is configured as DAISY_OUT for DIN Daisy
14d = DOUT is configured as DIN(LOOPBACK)
15d = Reserved
3DOUT_VALR/W0bDOUT output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
2-0DOUT_DRV[2:0]R/W010bDOUT output drive configuration.
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved; Don't use

7.1.14 INTF_CFG2 Register (Address = 0x11) [Reset = 0x80]

INTF_CFG2 is shown in Table 7-15.

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This register is the interface configuration register 2.

Table 7-15 INTF_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7PASI_DIN_ENR/W1bPrimary ASI DIN enable configuration.
0d = Primary ASI DIN is disabled
1d = Primary ASI DIN is enabled
6-4SASI_FSYNC_SEL[2:0]R/W000bSecondary ASI FSYNC select configuration.
0d = Secondary ASI disabled
1d = GPIO1
2d = GPI2A
3d = GPI1A
4d = Reserved
5d = Primary ASI FSYNC
6d to 7d = Reserved
3-1SASI_BCLK_SEL[2:0]R/W000bSecondary ASI BCLK select configuration.
0d = Secondary ASI disabled
1d = GPIO1
2d = GPI2A
3d = GPI1A
4d = Reserved
5d = Primary ASI BCLK
6d to 7d = Reserved
0RESERVEDR0bReserved bit; Write only reset value

7.1.15 INTF_CFG3 Register (Address = 0x12) [Reset = 0x00]

INTF_CFG3 is shown in Table 7-16.

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This register is the interface configuration register 3.

Table 7-16 INTF_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-5SASI_DIN_SEL[2:0]R/W000bSecondary ASI DIN select configuration.
0d = Seondary ASI DIN is disabled
1d = GPIO1
2d = GPI2A
3d = GPI1A
4d = DOUT
5d = Primary ASI DIN
6d to 7d = Reserved
4-2SASI_DIN2_SEL[2:0]R/W000bSeondary ASI DIN2 select configuration.
0d = Seondary ASI DIN2 is disabled
1d = GPIO1
2d = GPI2A
3d = GPI1A
4d = DOUT
5d = Primary ASI DIN
6d to 7d = Reserved
1-0RESERVEDR00bReserved bits; Write only reset values

7.1.16 INTF_CFG4 Register (Address = 0x13) [Reset = 0x00]

INTF_CFG4 is shown in Table 7-17.

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This register is the interface configuration register 3.

Table 7-17 INTF_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7PDM_CH1_SELR/W0bPDM select configuration for channel 1 of record path.
0d = Channel 1 is analog (ADC) type on the record path
1d = Channel 1 is digital (PDM) type on the record path
6PDM_CH2_SELR/W0bPDM select configuration for channel 2 of record path.
0d = Channel 2 is analog (ADC) type on the record path
1d = Channel 2 is digital (PDM) type on the record path
5PDMDIN1_EDGER/W0bPDMCLK latching edge used for channel 1 and channel 2 data.
0d = Channel 1 data are latched on the negative edge, channel 2 data are latched on the positive edge
1d = Channel 1 data are latched on the positive edge, channel 2 data are latched on the negative edge
4PDMDIN2_EDGER/W0bPDMCLK latching edge used for channel 3 and channel 4 data.
0d = Channel 3 data are latched on the negative edge, channel 4 data are latched on the positive edge
1d = Channel 3 data are latched on the positive edge, channel 4 data are latched on the negative edge
3-2PDM_DIN1_SEL[1:0]R/W00bPDM data channels 1 and 2 select configuration.
0d = PDM data channels 1 and 2 are disabled
1d = GPIO1
2d = GPI2A
3d = GPI1A
1-0PDM_DIN2_SEL[1:0]R/W00bPDM data channels 3 and 4 select configuration.
0d = PDM data channels 3 and 4 are disabled
1d = GPIO1
2d = GPI2A
3d = GPI1A

7.1.17 INTF_CFG5 Register (Address = 0x14) [Reset = 0x00]

INTF_CFG5 is shown in Table 7-18.

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This register is the interface configuration register 4.

Table 7-18 INTF_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
7PDM_DIN_SEL_OVRDR/W0bPDM data channels (1 and 2)/(3 and 4) select configuration override.
0d = No Override
1d = PDM_DIN1/2_SEL if configured as GPI1 will be overriden as DIN
6DOUT_WITH_DINR/W0bDOUT used as both ASI OUT and ASI IN
0d = DOUT based on DOUT_SEL
1d = DOUT used as both ASI OUT and ASI DIN
5-4PD_ADC_GPIO[1:0]R/W00bPower down ADC using GPIO select configuration.(ADC powered down if any one of the PD_ADC_GPIO/ADC_PDZ is configured power down)
0d = Power down ADC using GPIO is disabled
1d = Power down ADC using GPIO1
2d = Power down ADC using GPI2A
3d = Power down ADC using GPI1A
3-2RESERVEDR/W00bReserved bits; Write only reset values
1RESERVEDR/W0bReserved bit; Write only reset value
0RESERVEDR/W0bReserved bit; Write only reset value

7.1.18 INTF_CFG6 Register (Address = 0x15) [Reset = 0x00]

INTF_CFG6 is shown in Table 7-19.

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This register is the interface configuration register 5.

Table 7-19 INTF_CFG6 Register Field Descriptions
BitFieldTypeResetDescription
7-6EN_MBIAS_GPIO[1:0]R/W00bEnable MICBIAS using GPIO select configuration.
0d = Enable MICBIAS using GPIO is disabled
1d = Enable MICBIAS using GPIO1
2d = Enable MICBIAS using GPI2A
3d = Enable MICBIAS using GPI1A
5-4IADC_CONVST_GPIO[1:0]R/W00bIADC conversion start using GPIO select configuration.
0d = Enable IADC using GPIO is disabled
1d = Enable IADC using GPIO1
2d = Enable IADC using GPI2A
3d = Enable IADC using GPI1A
3-0RESERVEDR0000bReserved bits; Write only reset value

7.1.19 ASI_CFG0 Register (Address = 0x18) [Reset = 0x40]

ASI_CFG0 is shown in Table 7-20.

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This register is the ASI configuration register 0.

Table 7-20 ASI_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7PASI_DISR/W0bDisable or enable primary ASI (PASI).
0d = Primary ASI enabled
1d = Primary ASI disabled
6SASI_DISR/W1bDisable or enable secondary ASI (SASI).
0d = Secondary ASI enabled
1d = Secondary ASI disabled
5SASI_CFG_GANGR/W0bAll configurations of secondary ASI ganged with primary ASI.
0d = Secondary ASI has independent configurations
1d = Secondary ASI configurations same as primary ASI
4-3DAISY_EN[1:0]R/W00bDaisy chain feature enable (Daisy buffer length is 64, only 1 ASI with 1 DOUT AND DIN available)
0d = Daisy chain disabled
1d = PASI daisy chain enabled (Secondary ASI not available)
2d = SASI daisy chain enabled (Primary ASI not available)
3d = Reserved; Don't use
2-0DAISY_IN_SEL[2:0]R/W000bDaisy input select configuration.
0d = Daisy input disabled
1d = GPIO1
2d = GPI2A
3d = GPI1A
4d = Reserved
5d = DIN
6d to 7d = Reserved

7.1.20 ASI_CFG1 Register (Address = 0x19) [Reset = 0x00]

ASI_CFG1 is shown in Table 7-21.

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This register is the ASI configuration register 1.

Table 7-21 ASI_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6ASI_DOUT_CFG[1:0]R/W00bASI data output configuration.
0d = 1 data output for Primary ASI and 1 data output for Secondary ASI
1d = 2 data outputs for Primary ASI
2d = 2 data outputs for Secondary ASI
3d = Reserved; Don't use
5-4ASI_DIN_CFG[1:0]R/W00bASI data input configuration.
0d = 1 data input for Primary ASI and 1 data input for Secondary ASI
1d = 2 data inputs for Primary ASI
2d = 2 data inputs for Secondary ASI
3d = Reserved; Don't use
3RESERVEDR/W0bReserved bit; Write only reset value
2RESERVEDR/W0bReserved bit; Write only reset value
1RESERVEDR/W0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.21 PASI_CFG0 Register (Address = 0x1A) [Reset = 0x30]

PASI_CFG0 is shown in Table 7-22.

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This register is the ASI configuration register 0.

Table 7-22 PASI_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6PASI_FORMAT[1:0]R/W00bPrimary ASI protocol format.
0d = TDM mode
1d = I2S mode
2d = LJ (left-justified) mode
3d = Reserved; Don't use
5-4PASI_WLEN[1:0]R/W11bPrimary ASI word or slot length.
0d = 16 bits (Recommended this setting to be used with 10-kΩ input impedance configuration)
1d = 20 bits
2d = 24 bits
3d = 32 bits
3PASI_FSYNC_POLR/W0bASI FSYNC polarity (for PASI protocol only).
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
2PASI_BCLK_POLR/W0bASI BCLK polarity (for PASI protocol only).
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
1PASI_BUS_ERRR/W0bASI bus error detection.
0d = Enable bus error detection
1d = Disable bus error detection
0PASI_BUS_ERR_RCOVR/W0bASI bus error auto resume.
0d = Enable auto resume after bus error recovery
1d = Disable auto resume after bus error recovery and remain powered down until host configures the device

7.1.22 PASI_TX_CFG0 Register (Address = 0x1B) [Reset = 0x00]

PASI_TX_CFG0 is shown in Table 7-23.

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This register is the PASI TX configuration register 0.

Table 7-23 PASI_TX_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7PASI_TX_EDGER/W0bPrimary ASI data output (on the primary and secondary data pin) transmit edge.
0d = Default edge as per the protocol configuration setting in PASI_BCLK_POL
1d = Inverted following edge (half cycle delay) with respect to the default edge setting
6PASI_TX_FILLR/W0bPrimary ASI data output (on the primary and secondary data pin) for any unused cycles
0d = Always transmit 0 for unused cycles
1d = Always use Hi-Z for unused cycles
5PASI_TX_LSBR/W0bPrimary ASI data output (on the primary and secondary data pin) for LSB transmissions.
0d = Transmit the LSB for a full cycle
1d = Transmit the LSB for the first half cycle and Hi-Z for the second half cycle
4-3PASI_TX_KEEPER[1:0]R/W00bPrimary ASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled
1d = Bus keeper is always enabled
2d = Bus keeper is enabled during LSB transmissions only for one cycle
3d = Bus keeper is enabled during LSB transmissions only for one and half cycles
2PASI_TX_USE_INT_FSYNCR/W0bPrimary ASI uses internal FSYNC for output data generation in Controller mode configuration as applicable.
0d = Use external FSYNC for ASI protocol data generation
1d = Use internal FSYNC for ASI protocol data generation
1PASI_TX_USE_INT_BCLKR/W0bPrimary ASI uses internal BCLK for output data generation in Controller mode configuration.
0d = Use external BCLK for ASI protocol data generation
1d = Use internal BCLK for ASI protocol data generation
0PASI_TDM_PULSE_WIDTHR/W0bPrimary ASI fsync pulse width in TDM format. (Valid for Controller mode)
0d = Fsync pulse is 1 bclk period wide
1d = Fsync pulse is 2 bclk period wide

7.1.23 PASI_TX_CFG1 Register (Address = 0x1C) [Reset = 0x00]

PASI_TX_CFG1 is shown in Table 7-24.

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This register is the PASI TX configuration register 1.

Table 7-24 PASI_TX_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR000bReserved bits; Write only reset values
4-0PASI_TX_OFFSET[4:0]R/W00000bPrimary ASI output data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol
1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol
2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol
3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset assigned as per configuration
31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol

7.1.24 PASI_TX_CFG2 Register (Address = 0x1D) [Reset = 0x00]

PASI_TX_CFG2 is shown in Table 7-25.

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This register is the PASI TX configuration register 2.

Table 7-25 PASI_TX_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7PASI_TX_CH8_SELR/W0bPrimary ASI output channel 8 select.
0d = Primary ASI channel 8 output is on DOUT
1d = Primary ASI channel 8 output is on DOUT2
6PASI_TX_CH7_SELR/W0bPrimary ASI output channel 7 select.
0d = Primary ASI channel 7 output is on DOUT
1d = Primary ASI channel 7 output is on DOUT2
5PASI_TX_CH6_SELR/W0bPrimary ASI output channel 6 select.
0d = Primary ASI channel 6 output is on DOUT
1d = Primary ASI channel 6 output is on DOUT2
4PASI_TX_CH5_SELR/W0bPrimary ASI output channel 5 select.
0d = Primary ASI channel 5 output is on DOUT
1d = Primary ASI channel 5 output is on DOUT2
3PASI_TX_CH4_SELR/W0bPrimary ASI output channel 4 select.
0d = Primary ASI channel 4 output is on DOUT
1d = Primary ASI channel 4 output is on DOUT2
2PASI_TX_CH3_SELR/W0bPrimary ASI output channel 3 select.
0d = Primary ASI channel 3 output is on DOUT
1d = Primary ASI channel 3 output is on DOUT2
1PASI_TX_CH2_SELR/W0bPrimary ASI output channel 2 select.
0d = Primary ASI channel 2 output is on DOUT
1d = Primary ASI channel 2 output is on DOUT2
0PASI_TX_CH1_SELR/W0bPrimary ASI output channel 1 select.
0d = Primary ASI channel 1 output is on DOUT
1d = Primary ASI channel 1 output is on DOUT2

7.1.25 PASI_TX_CH1_CFG Register (Address = 0x1E) [Reset = 0x20]

PASI_TX_CH1_CFG is shown in Table 7-26.

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This register is the PASI TX Channel 1 configuration register.

Table 7-26 PASI_TX_CH1_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset values
5PASI_TX_CH1_CFGR/W1bPrimary ASI output channel 1 configuration.
0d = Primary ASI channel 1 output is in a tri-state condition
1d = Primary ASI channel 1 output corresponds to ADC/PDM Channel 1 data
4-0PASI_TX_CH1_SLOT_NUM[4:0]R/W00000bPrimary ASI output channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.1.26 PASI_TX_CH2_CFG Register (Address = 0x1F) [Reset = 0x21]

PASI_TX_CH2_CFG is shown in Table 7-27.

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This register is the PASI TX Channel 2 configuration register.

Table 7-27 PASI_TX_CH2_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset values
5PASI_TX_CH2_CFGR/W1bPrimary ASI output channel 2 configuration.
0d = Primary ASI channel 2 output is in a tri-state condition
1d = Primary ASI channel 2 output corresponds to ADC/PDM Channel 2 data
4-0PASI_TX_CH2_SLOT_NUM[4:0]R/W00001bPrimary ASI output channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.1.27 PASI_TX_CH3_CFG Register (Address = 0x20) [Reset = 0x02]

PASI_TX_CH3_CFG is shown in Table 7-28.

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This register is the PASI TX Channel 3 configuration register.

Table 7-28 PASI_TX_CH3_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5PASI_TX_CH3_CFG[1:0]R/W00bPrimary ASI output channel 3 configuration.
0d = Primary ASI channel 3 output is in a tri-state condition
1d = Primary ASI channel 3 output corresponds to PDM Channel 3 data
2d = Primary ASI channel 3 output corresponds to VBAT data
3d = Reserved
4-0PASI_TX_CH3_SLOT_NUM[4:0]R/W00010bPrimary ASI output channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.1.28 PASI_TX_CH4_CFG Register (Address = 0x21) [Reset = 0x03]

PASI_TX_CH4_CFG is shown in Table 7-29.

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This register is the PASI TX Channel 4 configuration register.

Table 7-29 PASI_TX_CH4_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5PASI_TX_CH4_CFG[1:0]R/W00bPrimary ASI output channel 4 configuration.
0d = Primary ASI channel 4 output is in a tri-state condition
1d = Primary ASI channel 4 output corresponds to PDM Channel 4 data
2d = Primary ASI channel 4 output corresponds to TEMP data
3d = Reserved
4-0PASI_TX_CH4_SLOT_NUM[4:0]R/W00011bPrimary ASI output channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.1.29 PASI_TX_CH5_CFG Register (Address = 0x22) [Reset = 0x04]

PASI_TX_CH5_CFG is shown in Table 7-30.

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This register is the PASI TX Channel 5 configuration register.

Table 7-30 PASI_TX_CH5_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5PASI_TX_CH5_CFG[1:0]R/W00bPrimary ASI output channel 5 configuration.
0d = Primary ASI channel 5 output is in a tri-state condition
1d = Primary ASI channel 5 output corresponds to ASI Input Channel 1 loopback data
Dont use
Dont use
4-0PASI_TX_CH5_SLOT_NUM[4:0]R/W00100bPrimary ASI output channel 5 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.1.30 PASI_TX_CH6_CFG Register (Address = 0x23) [Reset = 0x05]

PASI_TX_CH6_CFG is shown in Table 7-31.

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This register is the PASI TX Channel 6 configuration register.

Table 7-31 PASI_TX_CH6_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5PASI_TX_CH6_CFG[1:0]R/W00bPrimary ASI output channel 6 configuration.
0d = Primary ASI channel 6 output is in a tri-state condition
1d = Primary ASI channel 6 output corresponds to ASI Input Channel 2 loopback data
Dont use
Dont use
4-0PASI_TX_CH6_SLOT_NUM[4:0]R/W00101bPrimary ASI output channel 6 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.1.31 PASI_TX_CH7_CFG Register (Address = 0x24) [Reset = 0x06]

PASI_TX_CH7_CFG is shown in Table 7-32.

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This register is the PASI TX Channel 7 configuration register.

Table 7-32 PASI_TX_CH7_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5PASI_TX_CH7_CFG[1:0]R/W00bPrimary ASI output channel 7 configuration.
0d = Primary ASI channel 7 output is in a tri-state condition
1d = Primary ASI channel 7 output corresponds to {VBAT_WLby2, TEMP_WLby2}
Dont use
Dont use
4-0PASI_TX_CH7_SLOT_NUM[4:0]R/W00110bPrimary ASI output channel 7 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 14d = Slot assigned as per configuration
15d = TDM is slot 15 or I2S, LJ is left slot 15
16d = TDM is slot 16 or I2S, LJ is right slot 0
17d = TDM is slot 17 or I2S, LJ is right slot 1
18d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is right slot 15

7.1.32 PASI_RX_CFG0 Register (Address = 0x26) [Reset = 0x00]

PASI_RX_CFG0 is shown in Table 7-33.

Return to the Summary Table.

This register is the PASI RX configuration register 0.

Table 7-33 PASI_RX_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7PASI_RX_EDGER/W0bPrimary ASI data input (on the primary and secondary data pin) receive edge.
0d = Default edge as per the protocol configuration setting in PASI_BCLK_POL
1d = Inverted following edge (half cycle delay) with respect to the default edge setting
6PASI_RX_USE_INT_FSYNCR/W0bPrimary ASI uses internal FSYNC for input data latching in Controller mode configuration as applicable.
0d = Use external FSYNC for ASI protocol data latching
1d = Use internal FSYNC for ASI protocol data latching
5PASI_RX_USE_INT_BCLKR/W0bPrimary ASI uses internal BCLK for input data latching in Controller mode configuration.
0d = Use external BCLK for ASI protocol data latching
1d = Use internal BCLK for ASI protocol data latching
4-0PASI_RX_OFFSET[4:0]R/W00000bPrimary ASI data input MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol
1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of one BCLK cycle with respect to standard protocol
2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of two BCLK cycles with respect to standard protocol
3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset assigned as per configuration
31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left and right slot 0) offset of 31 BCLK cycles with respect to standard protocol

7.1.33 CLK_CFG0 Register (Address = 0x32) [Reset = 0x00]

CLK_CFG0 is shown in Table 7-34.

Return to the Summary Table.

This register is the clock configuration register 0.

Table 7-34 CLK_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-2PASI_SAMP_RATE[5:0]R/W000000bPrimary ASI sample rate configuration. -Typical (Allowed Range)
0d = Primary ASI sampling rate auto detected in the device
1d = 768000 (670320-791040)
2d = 614400 (536256-632832)
3d = 512000 (446880-527360)
4d = 438857 (383040-452022)
5d = 384000 (335160-395520)
6d = 341333 (297920-351573)
7d = 307200 (268128-316416)
8d = 256000 (223440-263680)
9d = 219429 (191520-226011)
10d = 192000 (167580-197760)
11d = 170667 (148960-175786)
12d = 153600 (134064-158208)
13d = 128000 (111720-131840)
14d = 109714 (95760-113005)
15d = 96000 (83790-98880)
16d = 85333 (74480-87893)
17d = 76800 (67032-79104)
18d = 64000 (55860-65920)
19d = 54857 (47880-56502)
20d = 48000 (41895-49440)
21d = 42667 (37240-43946)
22d = 38400 (33516-39552)
23d = 32000 (27930-32960)
24d = 27429 (23940-28251)
25d = 24000 (20947-24720)
26d = 21333 (18620-21973)
27d = 19200 (16758-19776)
28d = 16000 (13965-16480)
29d = 13714 (11970-14125)
30d = 12000 (10473-12360)
31d = 10667 (9310-10986)
32d = 9600 (8379-9888)
33d = 8000 (6982-8240)
34d = 6857 (5985-7062)
35d = 6000 (5236-6180)
36d = 5333 (4655-5493)
37d = 4800 (4189-4944)
38d = 4000 (3491-4120)
39d = 3429 (2992-3531)
40d = 3000 (2618-3090)
41d-63d = Reserved
1PASI_FS_RATE_NO_LIMR/W0bLimit sampling rate to standard audio sample rates only.
0d = Standard audio rates with 1% tolerance supported using auto mode
1d = Standard audio rates with 5% tolerance supported using auto mode
0CUSTOM_CLK_CFGR/W0bCustom clock configuration enable, all dividers and mux selects need to be manually configured.
0d = Auto clock configuration
1d = Custom clock configuration

7.1.34 CLK_CFG1 Register (Address = 0x33) [Reset = 0x00]

CLK_CFG1 is shown in Table 7-35.

Return to the Summary Table.

This register is the clock configuration register 1.

Table 7-35 CLK_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-2SASI_SAMP_RATE[5:0]R/W000000bSecondary ASI sample rate configuration. -Typical (Range)
0d = Secondary ASI sampling rate auto detected in the device
1d = 768000 (670320-791040)
2d = 614400 (536256-632832)
3d = 512000 (446880-527360)
4d = 438857 (383040-452022)
5d = 384000 (335160-395520)
6d = 341333 (297920-351573)
7d = 307200 (268128-316416)
8d = 256000 (223440-263680)
9d = 219429 (191520-226011)
10d = 192000 (167580-197760)
11d = 170667 (148960-175786)
12d = 153600 (134064-158208)
13d = 128000 (111720-131840)
14d = 109714 (95760-113005)
15d = 96000 (83790-98880)
16d = 85333 (74480-87893)
17d = 76800 (67032-79104)
18d = 64000 (55860-65920)
19d = 54857 (47880-56502)
20d = 48000 (41895-49440)
21d = 42667 (37240-43946)
22d = 38400 (33516-39552)
23d = 32000 (27930-32960)
24d = 27429 (23940-28251)
25d = 24000 (20947-24720)
26d = 21333 (18620-21973)
27d = 19200 (16758-19776)
28d = 16000 (13965-16480)
29d = 13714 (11970-14125)
30d = 12000 (10473-12360)
31d = 10667 (9310-10986)
32d = 9600 (8379-9888)
33d = 8000 (6982-8240)
34d = 6857 (5985-7062)
35d = 6000 (5236-6180)
36d = 5333 (4655-5493)
37d = 4800 (4189-4944)
38d = 4000 (3491-4120)
39d = 3429 (2992-3531)
40d = 3000 (2618-3090)
41d-63d = Reserved
1SASI_FS_RATE_NO_LIMR/W0bLimit sampling rate to standard audio sample rates only.
0d = Standard audio rates with 1% tolerance supported using auto mode
1d = Standard audio rates with 5% tolerance supported using auto mode
0RESERVEDR0bReserved bit; Write only reset value

7.1.35 CLK_CFG2 Register (Address = 0x34) [Reset = 0x40]

CLK_CFG2 is shown in Table 7-36.

Return to the Summary Table.

This register is the clock configuration register 2.

Table 7-36 CLK_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7PLL_DISR/W0bCustom/Auto clock mode PLL setting.
0d = PLL is always enabled in custom clk mode/PLL is enabled based on DSP MIPS requirement in auto clock mode
1d = PLL is disabled
6AUTO_PLL_FR_ALLOWR/W1bAllow the PLL to operate in fractional mode of operation.
0d = PLL fractional mode disabled
1d = PLL fractional mode allowed
5RESERVEDR/W0bReserved bit; Write only reset value
4RESERVEDR/W0bReserved bit; Write only reset value
3-1CLK_SRC_SEL[2:0]R/W000bInput clock source select.
0d = Primary ASI BCLK is the input clock source
1d = cclk synchronized with Primary ASI FSYNC is the input clock source
2d = Secondary ASI BCLK is the input clock source
3d = cclk synchronized with Secondary ASI FSYNC is the input clock source
4d = Fixed cclk frequency (used only in controller mode configuration)
5d = Internal oscillator clock is the input clock source
6d to 7d = Reserved
0RATIO_CLK_EDGER/W0bEdge selection for clock source ratio detection.
0d = Use rising edge of clock source to check ratio with primary or secondary FSYNC
1d = Use falling edge of clock source to check ratio with primary or secondary FSYNC

7.1.36 CNT_CLK_CFG0 Register (Address = 0x35) [Reset = 0x00]

CNT_CLK_CFG0 is shown in Table 7-37.

Return to the Summary Table.

This register is the controller mode clock configuration register 0.

Table 7-37 CNT_CLK_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6PDM_CLK_CFG[1:0]R/W00bPDM_CLK configurattion.
0d = PDM_CLK is 2.8224 MHz or 3.072 MHz
1d = PDM_CLK is 1.4112 MHz or 1.536 MHz
2d = PDM_CLK is 705.6 kHz or 768 kHz
3d = PDM_CLK is 5.6448 MHz or 6.144 MHz
5-0CCLK_FS_RATIO_MSB[5:0]R/W000000bMost significant bits for selecting the ratio between cclk and primary/secondary ASI FSYNC with which cclk is synchonized.
0d = Auto detect the ratio (assumption is cclk is synchronized with primary/secondary FSYNC)
1d to 16383d = Ratio as per configuration

7.1.37 CNT_CLK_CFG1 Register (Address = 0x36) [Reset = 0x00]

CNT_CLK_CFG1 is shown in Table 7-38.

Return to the Summary Table.

This register is the controller mode clock configuration register 1.

Table 7-38 CNT_CLK_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-0CCLK_FS_RATIO_LSB[7:0]R/W00000000bSelect the ratio between cclk and primary/secondary ASI FSYNC with which cclk is synchonized.
0d = Auto detect the ratio (assumption is cclk is synchronized with primary/secondary FSYNC)
1d to 16383d = Ratio as per configuration

7.1.38 CNT_CLK_CFG2 Register (Address = 0x37) [Reset = 0x20]

CNT_CLK_CFG2 is shown in Table 7-39.

Return to the Summary Table.

This register is the controller mode clock configuration register 2.

Table 7-39 CNT_CLK_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-5CCLK_FREQ_SEL[2:0]R/W001bThese bits select the CCLK input frequency (used only in controller mode configuration).
0d = 12 MHz
1d = 12.288 MHz
2d = 13 MHz
3d = 16 MHz
4d = 19.2 MHz
5d = 19.68 MHz
6d = 24 MHz
7d = 24.576 MHz
4PASI_CNT_CFGR/W0bPrimary ASI controller or target configuration
0d = Primary ASI in target configuration
1d = Primary ASI in controller configuration
3SASI_CNT_CFGR/W0bSecondary ASI controller or target configuration
0d = Secondary ASI in target configuration
1d = Secondary ASI in controller configuration
2RESERVEDR/W0bReserved bit; Write only reset value
1RESERVEDR/W0bReserved bit; Write only reset value
0FS_MODER/W0bSample rate setting (valid when the device is in controller mode). This is applicable for both PASI and SASI.
0d = sampling rate is a multiple (or submultiple) of 48 kHz
1d = sampling rate is a multiple (or submultiple) of 44.1 kHz

7.1.39 CNT_CLK_CFG3 Register (Address = 0x38) [Reset = 0x00]

CNT_CLK_CFG3 is shown in Table 7-40.

Return to the Summary Table.

This register is the controller mode clock configuration register 3.

Table 7-40 CNT_CLK_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7PASI_USE_INT_BCLK_FOR_FSYNCR/W0bUse internal BCLK for FSYNC generation in PASI during controller mode configuration.
0d = Use external BCLK for FSYNC generation
1d = Use internal BCLK for FSYNC generation
6PASI_INV_BCLK_FOR_FSYNCR/W0bInvert PASI BCLK polarity only for PASI FSYNC generation in controller mode configuration.
0d = Do not invert PASI BCLK polarity for PASI FSYNC generation
1d = Invert PASI BCLK polarity for PASI FSYNC generation
5-0PASI_BCLK_FS_RATIO_MSB[5:0]R/W000000bMSB bits for primary ASI BCLK to FSYNC ratio in controller mode.

7.1.40 CNT_CLK_CFG4 Register (Address = 0x39) [Reset = 0x00]

CNT_CLK_CFG4 is shown in Table 7-41.

Return to the Summary Table.

This register is the controller mode clock configuration register 4.

Table 7-41 CNT_CLK_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-0PASI_BCLK_FS_RATIO_LSB[7:0]R/W00000000bLSB byte for primary ASI BCLK to FSYNC ratio in controller mode.

7.1.41 CNT_CLK_CFG5 Register (Address = 0x3A) [Reset = 0x00]

CNT_CLK_CFG5 is shown in Table 7-42.

Return to the Summary Table.

This register is the controller mode clock configuration register 5.

Table 7-42 CNT_CLK_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
7SASI_USE_INT_BCLK_FOR_FSYNCR/W0bUse internal BCLK for FSYNC generation in SASI during controller mode configuration.
0d = Use external BCLK for FSYNC generation
1d = Use internal BCLK for FSYNC generation
6SASI_INV_BCLK_FOR_FSYNCR/W0bInvert SASI BCLK polarity only for SASI FSYNC generation in controller mode configuration.
0d = Do not invert SASI BCLK polarity for SASI FSYNC generation
1d = Invert SASI BCLK polarity for SASI FSYNC generation
5-0SASI_BCLK_FS_RATIO_MSB[5:0]R/W000000bMSB bits for secondary ASI BCLK to FSYNC ratio in controller mode.

7.1.42 CNT_CLK_CFG6 Register (Address = 0x3B) [Reset = 0x00]

CNT_CLK_CFG6 is shown in Table 7-43.

Return to the Summary Table.

This register is the controller mode clock configuration register 6.

Table 7-43 CNT_CLK_CFG6 Register Field Descriptions
BitFieldTypeResetDescription
7-0SASI_BCLK_FS_RATIO_LSB[7:0]R/W00000000bLSB byte for secondary ASI BCLK to FSYNC ratio in controller mode.

7.1.43 CLK_ERR_STS0 Register (Address = 0x3C) [Reset = 0x00]

CLK_ERR_STS0 is shown in Table 7-44.

Return to the Summary Table.

This register is the clock error and status register 0.

Table 7-44 CLK_ERR_STS0 Register Field Descriptions
BitFieldTypeResetDescription
7DSP_CLK_ERRR0bFlag indicating ratio error between FSYNC and selected clock source.
0d = No ratio error
1d = Ratio error between primary or secondary ASI FSYNC and selected clock source
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4SRC_RATIO_ERRR0bFlag indicating that SRC m:n ratio is unsupported. (not valid for custom m/n ratio config).
0d = m:n ratio supported
1d = Unsupported m:n ratio error
3DEM_RATE_ERRR0bFlag indicating that clock configuration does not allow valid DEM rate.
0d = No DEM clock rate error
1d = DEM clock rate error in selected clock configuration
2PDM_CLK_ERRR0bFlag indicating that clock configuration does not allow valid PDM clock generation.
0d = No PDM clock generation error
1d = PDM clock generation error in selected clock configuration
1RESET_ON_CLK_STOP_DET_STSR0bFlag indicating that audio clock source stopped for atleast 1ms.
0d = No audio clock source error
1d = Audio clock source stopped for atleast 1ms
0RESERVEDR0bReserved bit; Write only reset value

7.1.44 CLK_ERR_STS1 Register (Address = 0x3D) [Reset = 0x00]

CLK_ERR_STS1 is shown in Table 7-45.

Return to the Summary Table.

This register is the clock error and status register 1.

Table 7-45 CLK_ERR_STS1 Register Field Descriptions
BitFieldTypeResetDescription
7PASI_BCLK_FS_RATIO_ERRR0bFlag indicating PASI bclk fsync ratio error.
0d = No PASI bclk fsync ratio error
1d = PASI bclk fsync ratio error in selected clock configuration
6SASI_BCLK_FS_RATIO_ERRR0bFlag indicating SASI bclk fsync ratio error.
0d = No SASI bclk fsync ratio error
1d = SASI bclk fsync ratio error in selected clock configuration
5CCLK_FS_RATIO_ERRR0bFlag indicating CCLK fsync ratio error.
0d = No CCLK fsync ratio error
1d = CCLK fsync ratio error
4PASI_FS_ERRR0bFlag indicating PASI FS rate change or halt error.
0d = No PASI FS error
1d = PASI FS rate change or halt detected
3SASI_FS_ERRR0bFlag indicating SASI FS rate change or halt error.
0d = No SASI FS error
1d = SASI FS rate change or halt detected
2-0RESERVEDR000bReserved bits; Write only reset values

7.1.45 CLK_DET_STS0 Register (Address = 0x3E) [Reset = 0x00]

CLK_DET_STS0 is shown in Table 7-46.

Return to the Summary Table.

This register is the clock ratio detection register 0.

Table 7-46 CLK_DET_STS0 Register Field Descriptions
BitFieldTypeResetDescription
7-2PASI_SAMP_RATE_STS[5:0]R000000bPrimary ASI Sample rate detected status.
0d = Reserved
1d = 768000 (670320-791040)
2d = 614400 (536256-632832)
3d = 512000 (446880-527360)
4d = 438857 (383040-452022)
5d = 384000 (335160-395520)
6d = 341333 (297920-351573)
7d = 307200 (268128-316416)
8d = 256000 (223440-263680)
9d = 219429 (191520-226011)
10d = 192000 (167580-197760)
11d = 170667 (148960-175786)
12d = 153600 (134064-158208)
13d = 128000 (111720-131840)
14d = 109714 (95760-113005)
15d = 96000 (83790-98880)
16d = 85333 (74480-87893)
17d = 76800 (67032-79104)
18d = 64000 (55860-65920)
19d = 54857 (47880-56502)
20d = 48000 (41895-49440)
21d = 42667 (37240-43946)
22d = 38400 (33516-39552)
23d = 32000 (27930-32960)
24d = 27429 (23940-28251)
25d = 24000 (20947-24720)
26d = 21333 (18620-21973)
27d = 19200 (16758-19776)
28d = 16000 (13965-16480)
29d = 13714 (11970-14125)
30d = 12000 (10473-12360)
31d = 10667 (9310-10986)
32d = 9600 (8379-9888)
33d = 8000 (6982-8240)
34d = 6857 (5985-7062)
35d = 6000 (5236-6180)
36d = 5333 (4655-5493)
37d = 4800 (4189-4944)
38d = 4000 (3491-4120)
39d = 3429 (2992-3531)
40d = 3000 (2618-3090)
41d-63d = Reserved
1-0PLL_MODE_STS[1:0]R00bPLL usage status.
0d = PLL used in integer mode
1d = PLL used in fractional mode
2d = PLL not used
3d = Reserved

7.1.46 CLK_DET_STS1 Register (Address = 0x3F) [Reset = 0x00]

CLK_DET_STS1 is shown in Table 7-47.

Return to the Summary Table.

This register is the clock ratio detection register 1.

Table 7-47 CLK_DET_STS1 Register Field Descriptions
BitFieldTypeResetDescription
7-2SASI_SAMP_RATE_STS[5:0]R000000bSecondary ASI Sample rate detected status.
0d = Reserved
1d = 768000 (670320-791040)
2d = 614400 (536256-632832)
3d = 512000 (446880-527360)
4d = 438857 (383040-452022)
5d = 384000 (335160-395520)
6d = 341333 (297920-351573)
7d = 307200 (268128-316416)
8d = 256000 (223440-263680)
9d = 219429 (191520-226011)
10d = 192000 (167580-197760)
11d = 170667 (148960-175786)
12d = 153600 (134064-158208)
13d = 128000 (111720-131840)
14d = 109714 (95760-113005)
15d = 96000 (83790-98880)
16d = 85333 (74480-87893)
17d = 76800 (67032-79104)
18d = 64000 (55860-65920)
19d = 54857 (47880-56502)
20d = 48000 (41895-49440)
21d = 42667 (37240-43946)
22d = 38400 (33516-39552)
23d = 32000 (27930-32960)
24d = 27429 (23940-28251)
25d = 24000 (20947-24720)
26d = 21333 (18620-21973)
27d = 19200 (16758-19776)
28d = 16000 (13965-16480)
29d = 13714 (11970-14125)
30d = 12000 (10473-12360)
31d = 10667 (9310-10986)
32d = 9600 (8379-9888)
33d = 8000 (6982-8240)
34d = 6857 (5985-7062)
35d = 6000 (5236-6180)
36d = 5333 (4655-5493)
37d = 4800 (4189-4944)
38d = 4000 (3491-4120)
39d = 3429 (2992-3531)
40d = 3000 (2618-3090)
41d-63d = Reserved
1-0RESERVEDR00bReserved bits; Write only reset values

7.1.47 CLK_DET_STS2 Register (Address = 0x40) [Reset = 0x00]

CLK_DET_STS2 is shown in Table 7-48.

Return to the Summary Table.

This register is the clock ratio detection register 2.

Table 7-48 CLK_DET_STS2 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00bReserved bits; Write only reset values
5-0FS_CLKSRC_RATIO_DET_MSB_STS[5:0]R000000bMSB bits for primary ASI or secondary ASI FSYNC to clock source ratio detected.

7.1.48 CLK_DET_STS3 Register (Address = 0x41) [Reset = 0x00]

CLK_DET_STS3 is shown in Table 7-49.

Return to the Summary Table.

This register is the clock ratio detection register 3.

Table 7-49 CLK_DET_STS3 Register Field Descriptions
BitFieldTypeResetDescription
7-0FS_CLKSRC_RATIO_DET_LSB_STS[7:0]R00000000bLSB byte for primary ASI or secondary ASI FSYNC to clock source ratio detected.

7.1.49 INT_CFG Register (Address = 0x42) [Reset = 0x00]

INT_CFG is shown in Table 7-50.

Return to the Summary Table.

This regiser is the interrupt configuration register.

Table 7-50 INT_CFG Register Field Descriptions
BitFieldTypeResetDescription
7INT_POLR/W0bInterrupt polarity.
0b = Active low (IRQZ)
1b = Active high (IRQ)
6-5INT_EVENT[1:0]R/W00bInterrupt event configuration.
0d = INT asserts on any unmasked latched interrupts event
1d = INT asserts on any unmasked live interrupts event
2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any unmasked latched interrupts event
3d = INT asserts for 2 ms (typical) one time on each pulse for any unmasked interrupts event
4-3PD_ON_FLT_CFG[1:0]R/W00bPowerdown configuration during fault for chx and micbias.
0d = Faults are not considered for power down
1d = Only unmasked faults are considered for power down
2d = All faults are considered for powerdown
3d = Reserved
2LTCH_READ_CFGR/W0bInterrupt latch registers readback configuration.
0b = All interrupts can be read through the LTCH registers
1b = Only unmasked interrupts can be read through the LTCH registers
1PD_ON_FLT_RCV_CFGR/W0bConfiguration for Powerdown ADC channels on fault
0b = Auto recovery, ADC channels are re-powered up when fault goes away
1b = Manual recovery, ADC channels are not re-powered up when fault goes away
0LTCH_CLR_ON_READR/W0bCfgn for clearing LTCH register bits
0 = LTCH reg bits are cleared on reg read only if live status is zero
1 = LTCH reg bits are cleared on reg read irrespective of live status

7.1.50 ADC_DAC_MISC_CFG Register (Address = 0x4B) [Reset = 0x00]

ADC_DAC_MISC_CFG is shown in Table 7-51.

Return to the Summary Table.

Option to Mute ADC Channel in Overload Recovery Phase

Table 7-51 ADC_DAC_MISC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6RESERVEDR/W0bReserved bit; Write only reset value
5RESERVEDR/W0bReserved bit; Write only reset value
4ADC_CH1_MUTE_ON_OVRLDR/W0bMute ADC channel 1 while ADC1 is in Overload Recovery Phase
0b = Disable
1b = Enable
3ADC_CH2_MUTE_ON_OVRLDR/W0bMute ADC channel 2 while ADC2 is in Overload Recovery Phase
0b = Disable
1b = Enable
2-0RESERVEDR000bReserved bits; Write only reset values

7.1.51 PWR_TUNE_CFG0 Register (Address = 0x4E) [Reset = 0x00]

PWR_TUNE_CFG0 is shown in Table 7-52.

Return to the Summary Table.

This register is configuration register for power tune configuration.

Table 7-52 PWR_TUNE_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7ADC_CLK_BY2_MODER/W0bADC MOD CLK select configuration.
0d = MOD CLK 3MHz
1d = MOD CLK 1.5MHz
6ADC_CIC_ORDERR/W0bADC CIC order configuratoin.
0d = 5th order CIC
1d = 4th order CIC
5ADC_FIR_BYPASSR/W0bADC FIR bypass configuration.
0d = Bypass disable
1d = Bypass enable
4-3RESERVEDR/W00bReserved bits; Write only reset values
2ADC_LOW_PWR_FILTR/W0bLow Power filter configuration for ADC
0d = Disable
1d = Enable
1-0RESERVEDR00bReserved bits; Write only reset values

7.1.52 ADC_CH1_CFG0 Register (Address = 0x50) [Reset = 0x00]

ADC_CH1_CFG0 is shown in Table 7-53.

Return to the Summary Table.

This register is configuration register 0 for ADC channel 1.

Table 7-53 ADC_CH1_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6ADC_CH1_INSRC[1:0]R/W00bADC Channel 1 input configuration.
0d = Analog differential input
1d = Analog single-ended input
Dont use
Dont use
5-4RESERVEDR/W00bReserved bits; Write only reset values
3-2RESERVEDR/W00bReserved bits; Write only reset values
1ADC_CH1_FULLSCALE_VALR/W0bADC Channel 1 Fullscale value for VREF=2.75 V (applicable for the analog input).
0d = 10 Vrms differential
1d = 5 Vrms differential
0ADC_CH1_BW_MODER/W0bADC Channel 1 band-width selection. coupling (applicable for the analog input).
0d = audio band-width (24 kHz mode)
1d = wide band-width (96 kHz mode)

7.1.53 ADC_CH1_CFG2 Register (Address = 0x52) [Reset = 0xA1]

ADC_CH1_CFG2 is shown in Table 7-54.

Return to the Summary Table.

This register is configuration register 2 for ADC channel 1.

Table 7-54 ADC_CH1_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0ADC_CH1_DVOL[7:0]R/W10100001bChannel 1 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -80 dB
2d = Digital volume control is set to -79.5 dB
3d to 160d = Digital volume control is set as per configuration
161d = Digital volume control is set to 0 dB
162d = Digital volume control is set to 0.5 dB
163d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 46.5 dB
255d = Digital volume control is set to 47 dB

7.1.54 ADC_CH1_CFG3 Register (Address = 0x53) [Reset = 0x80]

ADC_CH1_CFG3 is shown in Table 7-55.

Return to the Summary Table.

This register is configuration register 3 for ADC channel 1.

Table 7-55 ADC_CH1_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-4ADC_CH1_FGAIN[3:0]R/W1000bADC channel 1 fine gain calibration.
0d = Fine gain is set to -0.8 dB
1d = Fine gain is set to -0.7 dB
2d = Fine gain is set to -0.6 dB
3d to 7d = Fine gain is set as per configuration
8d = Fine gain is set to 0 dB
9d = Fine gain is set to 0.1 dB
10d to 13d = Fine gain is set as per configuration
14d = Fine gain is set to 0.6 dB
15d = Fine gain is set to 0.7 dB
3-0RESERVEDR0000bReserved bits; Write only reset value

7.1.55 ADC_CH1_CFG4 Register (Address = 0x54) [Reset = 0x00]

ADC_CH1_CFG4 is shown in Table 7-56.

Return to the Summary Table.

This register is configuration register 4 for ADC channel 1.

Table 7-56 ADC_CH1_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-2ADC_CH1_PCAL[5:0]R/W000000bADC channel 1 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 62d = Phase calibration delay as per configuration
63d = Phase calibration delay is set to 63 cycles of the modulator clock
1-0PCAL_ANA_DIG_SEL[1:0]R/W00bPCAL support configuration.
0d = Pcal for both Ana-Dig supported
1d = Pcal for only Ana
2d = Pcal for only Dig
3d = Reserved

7.1.56 ADC_CH2_CFG0 Register (Address = 0x55) [Reset = 0x00]

ADC_CH2_CFG0 is shown in Table 7-57.

Return to the Summary Table.

This register is configuration register 0 for ADC channel 2.

Table 7-57 ADC_CH2_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6ADC_CH2_INSRC[1:0]R/W00bADC Channel 2 input configuration.
0d = Analog differential input
1d = Analog single-ended input
Dont use
Dont use
5-4RESERVEDR/W00bReserved bits; Write only reset values
3-2ADC_CH2_CM_TOL[1:0]R/W00bADC Channel 2 input coupling (applicable for the analog input).
0d = AC-coupled input with common mode variance tolerance supported 50 mVpp for single ended and 100 mVpp for differential configuration
1d = AC-coupled / DC-coupled input with common mode variance tolerance supported 500 mVpp for single ended and 1 Vpp for differential configuration (Expected SNR degradation of 1-2 dB)
2d = AC-coupled / DC-coupled input with common mode variance tolerance supported rail to rail (supply to ground) (Expected SNR degradation of 3-4 dB , High CMRR supported only in this case)
3d = Reserved
1ADC_CH2_FULLSCALE_VALR/W0bADC Channel 2 Fullscale value for VREF=2.75 V (applicable for the analog input).
0d = 10 Vrms differential
1d = 5 Vrms differential
0ADC_CH2_BW_MODER/W0bADC Channel 2 band-width selection. coupling (applicable for the analog input).
0d = audio band-width (24 kHz mode)
1d = wide band-width (96 kHz mode) (Supported only for 40-kΩ input impedance case)

7.1.57 ADC_CH2_CFG2 Register (Address = 0x57) [Reset = 0xA1]

ADC_CH2_CFG2 is shown in Table 7-58.

Return to the Summary Table.

This register is configuration register 2 for channel 2.

Table 7-58 ADC_CH2_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0ADC_CH2_DVOL[7:0]R/W10100001bChannel 1 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -80 dB
2d = Digital volume control is set to -79.5 dB
3d to 160d = Digital volume control is set as per configuration
161d = Digital volume control is set to 0 dB
162d = Digital volume control is set to 0.5 dB
163d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 46.5 dB
255d = Digital volume control is set to 47 dB

7.1.58 ADC_CH2_CFG3 Register (Address = 0x58) [Reset = 0x80]

ADC_CH2_CFG3 is shown in Table 7-59.

Return to the Summary Table.

This register is configuration register 3 for ADC Channel 2.

Table 7-59 ADC_CH2_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-4ADC_CH2_FGAIN[3:0]R/W1000bADC Channel 2 fine gain calibration.
0d = Fine gain is set to -0.8 dB
1d = Fine gain is set to -0.7 dB
2d = Fine gain is set to -0.6 dB
3d to 7d = Fine gain is set as per configuration
8d = Fine gain is set to 0 dB
9d = Fine gain is set to 0.1 dB
10d to 13d = Fine gain is set as per configuration
14d = Fine gain is set to 0.6 dB
15d = Fine gain is set to 0.7 dB
3-0RESERVEDR0000bReserved bits; Write only reset value

7.1.59 ADC_CH2_CFG4 Register (Address = 0x59) [Reset = 0x00]

ADC_CH2_CFG4 is shown in Table 7-60.

Return to the Summary Table.

This register is configuration register 4 for ADC Channel 2.

Table 7-60 ADC_CH2_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-2ADC_CH2_PCAL[5:0]R/W000000bADC Channel 2 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 62d = Phase calibration delay as per configuration
63d = Phase calibration delay is set to 63 cycles of the modulator clock
1-0RESERVEDR00bReserved bits; Write only reset value

7.1.60 ADC_CH3_CFG0 Register (Address = 0x5A) [Reset = 0x00]

ADC_CH3_CFG0 is shown in Table 7-61.

Return to the Summary Table.

This register is configuration register 0 for ADC channel 3.

Table 7-61 ADC_CH3_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7ADC_CH3_CLONER/W0bADC Channel 3 input configuration.
0d = clone disabled
1d = Channel 3 Digital Filter Input is generated same as Channel 1 Digital Filter Input (Cloned Input)
6-0RESERVEDR0000000bReserved bits; Write only reset value

7.1.61 ADC_CH3_CFG2 Register (Address = 0x5B) [Reset = 0xA1]

ADC_CH3_CFG2 is shown in Table 7-62.

Return to the Summary Table.

This register is configuration register 2 for ADC channel 3.

Table 7-62 ADC_CH3_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0ADC_CH3_DVOL[7:0]R/W10100001bChannel 3 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -80 dB
2d = Digital volume control is set to -79.5 dB
3d to 160d = Digital volume control is set as per configuration
161d = Digital volume control is set to 0 dB
162d = Digital volume control is set to 0.5 dB
163d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 46.5 dB
255d = Digital volume control is set to 47 dB

7.1.62 ADC_CH3_CFG3 Register (Address = 0x5C) [Reset = 0x80]

ADC_CH3_CFG3 is shown in Table 7-63.

Return to the Summary Table.

This register is configuration register 3 for ADC channel 3.

Table 7-63 ADC_CH3_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-4ADC_CH3_FGAIN[3:0]R/W1000bADC channel 3 fine gain calibration.
0d = Fine gain is set to -0.8 dB
1d = Fine gain is set to -0.7 dB
2d = Fine gain is set to -0.6 dB
3d to 7d = Fine gain is set as per configuration
8d = Fine gain is set to 0 dB
9d = Fine gain is set to 0.1 dB
10d to 13d = Fine gain is set as per configuration
14d = Fine gain is set to 0.6 dB
15d = Fine gain is set to 0.7 dB
3-0RESERVEDR0000bReserved bits; Write only reset value

7.1.63 ADC_CH3_CFG4 Register (Address = 0x5D) [Reset = 0x00]

ADC_CH3_CFG4 is shown in Table 7-64.

Return to the Summary Table.

This register is configuration register 4 for ADC channel 3.

Table 7-64 ADC_CH3_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-2ADC_CH3_PCAL[5:0]R/W000000bADC channel 3 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 62d = Phase calibration delay as per configuration
63d = Phase calibration delay is set to 63 cycles of the modulator clock
1-0RESERVEDR00bReserved bits; Write only reset value

7.1.64 ADC_CH4_CFG0 Register (Address = 0x5E) [Reset = 0x00]

ADC_CH4_CFG0 is shown in Table 7-65.

Return to the Summary Table.

This register is configuration register 0 for ADC Channel 4.

Table 7-65 ADC_CH4_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7ADC_CH4_CLONER/W0bADC Channel 4 input configuration.
0d = clone disabled
1d = Channel 4 Digital Filter Input is generated same as Channel 2 Digital Filter Input (Cloned Input)
6-0RESERVEDR0000000bReserved bits; Write only reset value

7.1.65 ADC_CH4_CFG2 Register (Address = 0x5F) [Reset = 0xA1]

ADC_CH4_CFG2 is shown in Table 7-66.

Return to the Summary Table.

This register is configuration register 2 for channel 4.

Table 7-66 ADC_CH4_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-0ADC_CH4_DVOL[7:0]R/W10100001bChannel 4 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -80 dB
2d = Digital volume control is set to -79.5 dB
3d to 160d = Digital volume control is set as per configuration
161d = Digital volume control is set to 0 dB
162d = Digital volume control is set to 0.5 dB
163d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 46.5 dB
255d = Digital volume control is set to 47 dB

7.1.66 ADC_CH4_CFG3 Register (Address = 0x60) [Reset = 0x80]

ADC_CH4_CFG3 is shown in Table 7-67.

Return to the Summary Table.

This register is configuration register 3 for ADC Channel 4.

Table 7-67 ADC_CH4_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-4ADC_CH4_FGAIN[3:0]R/W1000bADC Channel 4 fine gain calibration.
0d = Fine gain is set to -0.8 dB
1d = Fine gain is set to -0.7 dB
2d = Fine gain is set to -0.6 dB
3d to 7d = Fine gain is set as per configuration
8d = Fine gain is set to 0 dB
9d = Fine gain is set to 0.1 dB
10d to 13d = Fine gain is set as per configuration
14d = Fine gain is set to 0.6 dB
15d = Fine gain is set to 0.7 dB
3-0RESERVEDR0000bReserved bits; Write only reset value

7.1.67 ADC_CH4_CFG4 Register (Address = 0x61) [Reset = 0x00]

ADC_CH4_CFG4 is shown in Table 7-68.

Return to the Summary Table.

This register is configuration register 4 for ADC Channel 4.

Table 7-68 ADC_CH4_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-2ADC_CH4_PCAL[5:0]R/W000000bADC Channel 4 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 62d = Phase calibration delay as per configuration
63d = Phase calibration delay is set to 63 cycles of the modulator clock
1-0RESERVEDR00bReserved bits; Write only reset value

7.1.68 DSP_CFG0 Register (Address = 0x72) [Reset = 0x18]

DSP_CFG0 is shown in Table 7-69.

Return to the Summary Table.

This register is the digital signal processor (DSP) configuration register 0.

Table 7-69 DSP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6ADC_DSP_DECI_FILT[1:0]R/W00bADC channel decimation filter response.
0d = Linear phase
1d = Low latency
2d = Ultra-low latency
3d = Reserved; Don't use
5-4ADC_DSP_HPF_SEL[1:0]R/W01bADC channel high-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default coefficient values in P10_R120-127 and P11_R8-11 set as the all-pass filter
1d = HPF with a cutoff of 0.00002 x fS (1 Hz at fS = 48 kHz) is selected
2d = HPF with a cutoff of 0.00025 x fS (12 Hz at fS = 48 kHz) is selected
3d = HPF with a cutoff of 0.002 x fS (96 Hz at fS = 48 kHz) is selected
3-2ADC_DSP_BQ_CFG[1:0]R/W10bNumber of biquads per ADC channel configuration.
0d = No biquads per channel; biquads are all disabled
1d = 1 biquad per channel
2d = 2 biquads per channel
3d = 3 biquads per channel
1ADC_DSP_DISABLE_SOFT_STEPR/W0bADC Soft-stepping disable during DVOL change, mute, and unmute.
0d = Soft-stepping enabled
1d = Soft-stepping disabled
0ADC_DSP_DVOL_GANGR/W0bDVOL control ganged across ADC channels.
0d = Each channel has its own DVOL CTRL settings as programmed in the ADC_CHx_DVOL bits
1d = All active channels must use the channel 1 DVOL setting (ADC_CH1_DVOL) irrespective of whether channel 1 is turned on or not

7.1.69 CH_EN Register (Address = 0x76) [Reset = 0xCC]

CH_EN is shown in Table 7-70.

Return to the Summary Table.

This register is the channel enable configuration register.

Table 7-70 CH_EN Register Field Descriptions
BitFieldTypeResetDescription
7IN_CH1_ENR/W1bInput channel 1 enable setting.
0d = Input channel 1 is disabled
1d = Input channel 1 is enabled
6IN_CH2_ENR/W1bInput channel 2 enable setting.
0d = Input channel 2 is disabled
1d = Input channel 2 is enabled
5IN_CH3_ENR/W0bInput channel 3 enable setting.
0d = Input channel 3 is disabled
1d = Input channel 3 is enabled
4IN_CH4_ENR/W0bInput channel 4 enable setting.
0d = Input channel 4 is disabled
1d = Input channel 4 is enabled
3RESERVEDR/W1bReserved bit; Write only reset value
2RESERVEDR/W1bReserved bit; Write only reset value
1RESERVEDR/W0bReserved bit; Write only reset value
0RESERVEDR/W0bReserved bit; Write only reset value

7.1.70 DYN_PUPD_CFG Register (Address = 0x77) [Reset = 0x00]

DYN_PUPD_CFG is shown in Table 7-71.

Return to the Summary Table.

This register is the power-up configuration register.

Table 7-71 DYN_PUPD_CFG Register Field Descriptions
BitFieldTypeResetDescription
7ADC_DYN_PUPD_ENR/W0bDynamic channel power-up, power-down enable for record path.
0d = Channel power-up, power-down is not supported if any channel recording is on
1d = Channel can be powered up or down individually, even if channel recording is on
6ADC_DYN_MAXCH_SELR/W0bDynamic mode maximum channel select configuration for record path.
0d = Channel 1 and channel 2 are used with dynamic channel power-up, power-down feature enabled
1d = Channel 1 to channel 4 are used with dynamic channel power-up, power-down feature enabled
5RESERVEDR/W0bReserved bit; Write only reset value
4RESERVEDR/W0bReserved bit; Write only reset value
3DYN_PUPD_ADC_PDM_DIFF_CLKR/W0bDynamic power-up power-down with different adc mod clock and pdm clock configuration.
0d = Same ADC MOD CLK and PDM CLK in dynamic pupd
1d = Different ADC MOD CLK and PDM CLK in dynamic pupd
2-0RESERVEDR000bReserved bits; Write only reset value

7.1.71 PWR_CFG Register (Address = 0x78) [Reset = 0x00]

PWR_CFG is shown in Table 7-72.

Return to the Summary Table.

This register is the power-up configuration register.

Table 7-72 PWR_CFG Register Field Descriptions
BitFieldTypeResetDescription
7ADC_PDZR/W0bPower control for ADC and PDM channels.
0d = Power down all ADC and PDM channels
1d = Power up all enabled ADC and PDM channels
6RESERVEDR/W0bReserved bit; Write only reset value
5MICBIAS_PDZR/W0bPower control for MICBIAS.
0d = Power down MICBIAS
1d = Power up MICBIAS
4RESERVEDR0bReserved bit; Write only reset value
3UAD_ENR/W0bEnable ultrasound activity detection (UAD) algorithm.
0d = UAD is disabled
1d = UAD is enabled
2VAD_ENR/W0bEnable voice activity detection (VAD) algorithm.
0d = VAD is disabled
1d = VAD is enabled
1RESERVEDR/W0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.72 DEV_STS0 Register (Address = 0x79) [Reset = 0x00]

DEV_STS0 is shown in Table 7-73.

Return to the Summary Table.

This register is the device status value register 0.

Table 7-73 DEV_STS0 Register Field Descriptions
BitFieldTypeResetDescription
7IN_CH1_STATUSR0bADC or PDM channel 1 power status.
0d = ADC or PDM channel is powered down
1d = ADC or PDM channel is powered up
6IN_CH2_STATUSR0bADC or PDM channel 2 power status.
0d = ADC or PDM channel is powered down
1d = ADC or PDM channel is powered up
5IN_CH3_STATUSR0bADC or PDM channel 1 power status.
0d = ADC or PDM channel is powered down
1d = ADC or PDM channel is powered up
4IN_CH4_STATUSR0bADC or PDM channel 2 power status.
0d = ADC or PDM channel is powered down
1d = ADC or PDM channel is powered up
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.73 DEV_STS1 Register (Address = 0x7A) [Reset = 0x80]

DEV_STS1 is shown in Table 7-74.

Return to the Summary Table.

This register is the device status value register 1.

Table 7-74 DEV_STS1 Register Field Descriptions
BitFieldTypeResetDescription
7-5MODE_STS[2:0]R100bDevice mode status.
0-3d = Reserved
4d = Device is in sleep mode or software shutdown mode
5d = Reserved
6d = Device is in active mode with all record and playback channels turned off
7d = Device is in active mode with at least one record or playback channel turned on
4PLL_STSR0bPLL status.
0d = PLL is not enabled
1d = PLL is enabled
3MICBIAS_STSR0bMICBIAS status.
0d = MICBIAS is disabled
1d = MICBIAS is enabled
2BOOST_STSR0bBoost status.
0d = Boost is disabled
1d = Boost is enabled
1CHx_PD_FLT_STSR0bStatus for PD on INxx Analog inputs faults
0d = No ADC Channel is Powered Down due to fault/s on Analog inputs INxx
1d = Some ADC Channel is Powered Down due to fault/s on Analog inputs INxx
0ALL_CHx_PD_FLT_STSR0bStatus for PD on Micbias faults
0d = No ADC Channel is Powered Down due to fault/s related to Micbias
1d = All ADC Channels are Powered Down due to fault/s related to Micbias

7.1.74 I2C_CKSUM Register (Address = 0x7E) [Reset = 0x00]

I2C_CKSUM is shown in Table 7-75.

Return to the Summary Table.

This register returns the I2C transactions checksum value.

Table 7-75 I2C_CKSUM Register Field Descriptions
BitFieldTypeResetDescription
7-0I2C_CKSUM[7:0]R/W00000000bThese bits return the I2C transactions checksum value. Writing to this register resets the checksum to the written value. This register is updated on writes to other registers on all pages.