JAJSOO3A October   2014  – June 2022 TMP75B-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 Temperature Limits and Alert
      3. 7.3.3 Serial Interface
        1. 7.3.3.1  Bus Overview
        2. 7.3.3.2  Serial Bus Address
        3. 7.3.3.3  Writing and Reading Operation
        4. 7.3.3.4  Target-Mode Operations
          1. 7.3.3.4.1 Target Receiver Mode:
          2. 7.3.3.4.2 Target Transmitter Mode:
        5. 7.3.3.5  SMBus Alert Function
        6. 7.3.3.6  General Call
        7. 7.3.3.7  High-Speed (Hs) Mode
        8. 7.3.3.8  Timeout Function
        9. 7.3.3.9  Two-Wire Timing
        10. 7.3.3.10 Two-Wire Timing Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous-Conversion Mode
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 One-Shot Mode
    5. 7.5 Programming
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3.1 Bus Overview

The device that initiates the transfer is called a controller, and the devices controlled by the controller are targets. The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions.

To address a specific device, initiate a start condition by pulling the data line (SDA) from a high to a low logic level while SCL is high. All targets on the bus shift in the target address byte; the last bit indicates whether a read or write operation follows. During the ninth clock pulse, the target being addressed responds to the controller by generating an acknowledge bit and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted as a start or stop signal.

After all data have been transferred, the controller generates a stop condition indicated by pulling SDA from low to high, while SCL is high.