JAJSO66A December   2023  – January 2024 TPS61289

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Bidirectional Operation Configuration
      2. 6.3.2 VCC Power Supply
      3. 6.3.3 VHIGH and VCC Undervoltage Lockout (UVLO)
      4. 6.3.4 Enable and Programmable EN/UVLO
      5. 6.3.5 Switching Frequency
      6. 6.3.6 Programmable Switching Peak and Valley Current Limit
      7. 6.3.7 External Clock Synchronization
      8. 6.3.8 VHIGH Overvoltage Protection
      9. 6.3.9 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Bootstrap Capacitor Selection
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 MOSFET Selection
        4. 7.2.2.4 VLOW/VHIGH Output Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2.4 VLOW/VHIGH Output Capacitor Selection

For small output voltage ripple, TI recommends a low-ESR output capacitor like a ceramic capacitor. Higher capacitor values or parallel with aluminum electrolytic capacitors can be used to improve the load transient response. Take care when evaluating the derating of the capacitor under DC bias. The bias can significantly reduce capacitance. Ceramic capacitors can lose most of their capacitance at rated voltage. Therefore, leave margin on the voltage rating to provide adequate effective capacitance. From the required output voltage ripple, use the following equations to calculate the minimum required effective capacitance COUT.

Equation 8. V r i p p l e _ d i s = V O U T - V I N _ M I N × I O U T V O U T × f S W × C O U T
Equation 9. V r i p p l e _ E S R = I L p e a k × R C _ E S R

where

  • Vripple_dis is output voltage ripple caused by charging and discharging of the output capacitor.
  • Vripple_ESR is output voltage ripple caused by ESR of the output capacitor.
  • VIN_MIN is the minimum input voltage.
  • VOUT is the output voltage.
  • IOUT is the output current.
  • ILpeak is the peak current of the inductor.
  • ƒSW is the converter switching frequency.
  • RC_ESR is the ESR of the output capacitors.
Note:

DC bias effect: High-capacitance ceramic capacitors have a DC bias effect, which has a strong influence on the final effective capacitance. Therefore, the right capacitor value must be chosen carefully. The differences between the rated capacitor value and the effective capacitance result from package size and voltage rating in combination with material. A 10V rated 0805 capacitor with 10μF can have an effective capacitance of less than 5μF at an output voltage of 5V.