JAJSO66A December   2023  – January 2024 TPS61289

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Bidirectional Operation Configuration
      2. 6.3.2 VCC Power Supply
      3. 6.3.3 VHIGH and VCC Undervoltage Lockout (UVLO)
      4. 6.3.4 Enable and Programmable EN/UVLO
      5. 6.3.5 Switching Frequency
      6. 6.3.6 Programmable Switching Peak and Valley Current Limit
      7. 6.3.7 External Clock Synchronization
      8. 6.3.8 VHIGH Overvoltage Protection
      9. 6.3.9 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Bootstrap Capacitor Selection
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 MOSFET Selection
        4. 7.2.2.4 VLOW/VHIGH Output Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 14-Pin RZP VQFN Package (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NUMBER
ILIM 1 I Programmable switching peak/valley current limit. An external resistor must be connected between this pin and the AGND pin.
FB 2 I For bidirectional operation, connect to the center tap of a resistor divider to make the VFB = 0.7V to 0.8V.
COMP 3 I External loop compensation signal input pin.
MODE 4 I Mode selection pin, this pin must not be floating.

MODE = logic high, buck mode.

MODE = logic low, boost mode.
VHIGH 5 P High voltage side pin.
SW 6 P The switching node pin. This pin is connected to the drain of the external low-side MOSFET and the source of the internal high-side MOSFET.
BOOT 7 O Power supply for the high-side MOSFET gate driver. A ceramic capacitor of 0.1μF to 1.0μF and a 5.6V Zener diode must be connected between this pin and the SW pin.
PGND 8 G Power ground of external low side MOSFET. Source of external low side MOSFET must be connected to this pin.
DRV 9 O Gate driver output for external low-side MOSFET.
M/SYNC 10 I When the M/SYNC pin is short to ground or floating, the device works with internal configured switching frequency. When a valid clock signal is applied to this pin, the switching frequency of the device is forced to the external clock.
VCC 11 O Output of the internal regulator. A ceramic capacitor of more than 1.0µF is required between this pin and AGND.
VLOW 12 P Low voltage side pin.
EN/UVLO 13 I Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and puts the device into shutdown mode. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a resistor divider. This pin must not be left floating and must be terminated.
AGND 14 G Analog signal ground.
(1) I = Input, O = Output, G = Ground, P = Power.