JAJSRG7 September   2023 TPS6521905-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1 Converter
    7. 6.7  BUCK2, BUCK3 Converter
    8. 6.8  General Purpose LDOs (LDO1, LDO2)
    9. 6.9  General Purpose LDOs (LDO3, LDO4)
    10. 6.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 6.11 Voltage and Temperature Monitors
    12. 6.12 I2C Interface
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 機能ブロック図
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  Reset to SoC (nRSTOUT)
      5. 7.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 7.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Linear Regulators (LDO1 through LDO4)
      7. 7.3.7  Interrupt Pin (nINT)
      8. 7.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 7.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 7.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 7.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 7.3.12 I2C-Compatible Interface
        1. 7.3.12.1 Data Validity
        2. 7.3.12.2 Start and Stop Conditions
        3. 7.3.12.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 Fault Handling
    5. 7.5 Multi-PMIC Operation
    6. 7.6 NVM Programming
      1. 7.6.1 TPS6521905-Q1 default NVM settings
      2. 7.6.2 NVM programming in Initialize State
      3. 7.6.3 NVM Programming in Active State
    7. 7.7 User Registers
    8. 7.8 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Example
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 8.2.3.2 LDO1, LDO2 Design Procedure
        3. 8.2.3.3 LDO3, LDO4 Design Procedure
        4. 8.2.3.4 VSYS, VDD1P8
        5. 8.2.3.5 Digital Signals Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6.2 NVM programming in Initialize State

NVM programming can be done in Initialize or Active state. The current state can be read from STATE bits (bits 4-3) in POWER_UP_STATUS_REG register. After a valid supply is connected to VSYS, the device goes to Initialize state and loads the default NVM content into the register map. Loading the NVM content takes approximately 2.3ms. Once register map is loaded with the default settings, PMIC is ready for NVM programming. Figure 7-18 shows the steps required to reprogram the NVM in Initialize state while the PMIC rails are OFF. The process starts with enabling the oscillator for I2C communication. This command also disables the rails active discharge. Then, update the NVM register fields and save the new settings into the memory. Several register settings are available to indicate the status of an I2C command. For example, Register field CUST_PROG_DONE (bit 5, address 0x34) indicates the status of the NVM programming after CUST_PROG_CMD is executed. Similarly, register field CUST_NVM_VERIFY_DONE (bit 6, address 0x34) indicates the status (not the result) of the NVM verification after CUST_NVM_VERIFY_CMD is executed.

Note: For in-circuit programming, it is recommended to temporarily disconnect the PMIC rail from the I2C lines while using an external 3.3V to re-program the NVM. Since regulators are disabled in Initialize state, their active discharge is enabled. This active discharge feature can dissipate power from the external 3.3V supply if it is sharing the same voltage node with a PMIC rail. If disconnecting the PMIC rail is not an option, then the EN_OSC_DIY command must be send immediately (within ~10 seconds) after the 3.3V VIO is supplied in Initialize state. Discharge is disabled after the EN_OSC_DIY command is received.
GUID-20230625-SS0I-GQD3-TWR9-J4DNK04P8SHK-low.svg Figure 7-18 NVM Programming steps