JAJSRG7 September   2023 TPS6521905-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1 Converter
    7. 6.7  BUCK2, BUCK3 Converter
    8. 6.8  General Purpose LDOs (LDO1, LDO2)
    9. 6.9  General Purpose LDOs (LDO3, LDO4)
    10. 6.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 6.11 Voltage and Temperature Monitors
    12. 6.12 I2C Interface
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 機能ブロック図
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  Reset to SoC (nRSTOUT)
      5. 7.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 7.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Linear Regulators (LDO1 through LDO4)
      7. 7.3.7  Interrupt Pin (nINT)
      8. 7.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 7.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 7.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 7.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 7.3.12 I2C-Compatible Interface
        1. 7.3.12.1 Data Validity
        2. 7.3.12.2 Start and Stop Conditions
        3. 7.3.12.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 Fault Handling
    5. 7.5 Multi-PMIC Operation
    6. 7.6 NVM Programming
      1. 7.6.1 TPS6521905-Q1 default NVM settings
      2. 7.6.2 NVM programming in Initialize State
      3. 7.6.3 NVM Programming in Active State
    7. 7.7 User Registers
    8. 7.8 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Example
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 8.2.3.2 LDO1, LDO2 Design Procedure
        3. 8.2.3.3 LDO3, LDO4 Design Procedure
        4. 8.2.3.4 VSYS, VDD1P8
        5. 8.2.3.5 Digital Signals Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 NVM Programming

The TPS6521905-Q1 is part of Texas Instruments user-programmable PMICs. This device integrates a NVM memory that provides the ability to configure the power and digital resources. The NVM programming feature makes the TPS6521905-Q1 PMIC a flexible power solution to meet the requirements from different processors and SoCs. Programmable NVM fields include output voltages, sequencing, monitoring thresholds, GPIO control among others. OTA (Over The Air) programming, where EEPROM can be change directly without changing register settings, is not supported. Re-programming the NVM is done by first writing to the register map through the serial interface (I2C) and then saving the register settings into the NVM. The EEPROM of a device can only be programmed up to 1000 times. EEPROM values can only be changed if the input voltage (VSYS) is equal or greater than 3.3 V. The I2C pins must be pulled up to a 3.3V supply. At a high level, the programming flow can be described in three steps: determine your system requirements, update the register settings, save the new values into the NVM memory. Detailed information regarding the programming of the non-volatile memory is available in the TPS65219 NVM Programming Guide located under Technical documentation in the TPS6521905-Q1 product page on ti.com.

Note: Writing 0x0A to register address 0x34 commits the current register settings to NVM memory so they become the new power-up defaults. Customer programmable registers correspond to addresses 0x0 to 0x27. Only bits marked with (X) in the reset column of the register map have EEPROM programmable default settings. All other bits keep the factory settings listed in the register map.