An OFF-request or a shut-down-fault triggers the power-down sequence. The OFF-request can be triggered by a falling edge on EN/PB/VSENSE if configured for EN or VSENSE respectively a long press of the push-button if configured as PB or by an I2C-command to I2C_OFF_REQ in MFP_CTRL register. This bit self-clears.

An I2C-triggered shut-down requires a renewed ON-request on the EN/PB/VSENSE pin. In case of EN- or VSENSE-configuration, a low-going edge followed by a high-going-edge is required on the EN/PB/VSENSE-pin. The falling-edge deglitch time for EN or VSENSE configuration t_{DEGL_EN/VSENSE_I2C} is shorter than the deglitch-time for pin-induced OFF-requests (t_{DEGL_EN_Fall} and t_{DEGL_VSENSE_Fall}). The deglitch-times for PB-configuration remain.

In many cases, the power-down sequence follows the reverse power-up sequence. In some applications, all rails can be required to shut down at the same time with no delay between rails or require wait-times to allow discharging of rail.

The power-down sequence is configured as follows:

• The slot (respectively the position in the sequence) for each rail and GPO1, GPO2, GPIO, and nRSTOUT is defined using the corresponding *_SEQUENCE_SLOT registers, the four MSB for the ON-sequence, the four LSB for the down-sequencing.
• The duration of each slot is defined in the POWER_DOWN_SLOT_DURATION_x registers and can be configured as 0 ms, 1.5 ms, 3 ms or 10 ms. In total, 16 slots can be configured, allowing the sequence to span over multiple TPS6521905-Q1-devices if more rails need to be supported.
• In addition to the slot-duration, the power-down sequence is also gated by the previous rail being discharged below the SCG-threshold, unless active discharge is disabled on the previous rail. If that does not occur, the power-down of subsequent rails is paused. To allow for power-down in case of biased or shorted rails, the sequence continues despite an incomplete discharge of the previous rail after eight times the slot-duration (or 12 ms in case of slot-duration of 0 ms).
• To bypass the discharge-check, set the bit BYPASS_RAILS_DISCHARGED_CHECK in register GENERAL_CONFIG to '1'.

Active discharge is enabled by default and not NVM based. Thus, if desired, discharge need to be disabled after each VSYS-power-cycle. During RESET or OFF-request, the discharge configuration is not reset, as long as VSYS is present. However, in INITIALIZE state and prior to the power-up-sequence, all rails get discharged, regardless of the setting.

During the power-down-sequence, non-EEPROM-backed bits get reset, with the exception of unmasked interrupt bits and *_DISCHARGE_EN bits.

Below graphic shows the power-down-sequence for NVM-ID 0x01, revision 0x2 as an example:

Figure 7-3 Power-down sequencing (example)