4 Pin Configuration and Functions

Figure 4-1 45-Pin QFM-MOY Package (Top View)

Figure 4-2 45-Pin QFM-MOY Package (Bottom View)

Table 4-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
PGND	1, 4, 17, 23, 39, 42, 44	—	Power stage ground return. Pins 42 and 44 also act as the thermal pad of the device.
VOSNS	2	I	The positive input of the remote sense amplifier. For a standalone device or a loop controller device in a multi-phase configuration, connect the VOSNS pin to the output voltage at the load. For the loop follower device in a multi-phase configuration, the remote sense amplifier is not required for output voltage sensing or regulation and this pin can be left floating. If used to monitor another voltage with the Phased READ_VOUT command, VOSNS must be maintained between 0V and 0.75V with a < 1kΩ resistor divider due to the internal resistance to GOSNS, which is connected to BP1V5.
GOSNS/FLWR	3	I	The negative input of the remote sense amplifier for a loop controller device or pull up high to indicate loop follower. For a standalone device or a loop controller device in a multi-phase configuration, connect the GOSNS pin to the ground at the load. For the loop follower device in a multi-phase configuration, the GOSNS pin must be pulled up to BP1V5 to indicate the device is a loop follower.
BP1V5	5	O	Output of the 1.5V internal regulator for MSEL,VSEL, and ADRSEL pins. No external bypassing required. Not designed to power other circuits.
SMB_ALRT	6	O	SMBus alert pin. See SMBus specification.
PMB_CLK	7	I	PMBus CLK pin. See the Current PMBus Specifications.
PMB_DATA	8	I/O	PMBus DATA pin. See the Current PMBus Specifications.
PGD/RST	9	I/O	Open-drain power good or (21h) VOUT_COMMAND RESET#. As determined by user-programmable RESET# bit in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS). The default pin function is an open-drain power-good indicator. When configured as RESET#, an internal pullup can be enabled or disabled by the PULLUP# bit in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS).
BCX_DATA	10	I/O	Data for back-channel communications between stacked devices
BCX_CLK	11	I/O	Clock for back-channel communications between stacked devices
VSHARE	12	I/O	Voltage sharing signal for multi-phase operation. For a standalone device, the VSHARE pin must be left floating. VSHARE can be bypassed to AGND with up to 50pF of capacitance.
MSEL1	13	I	Connect this pin to a 1% tolerance or better resistor divider between BP1V5and AGND for different options of switching frequency and internal compensation parameters. See Programming MSEL1.
ADRSEL	14	I	Connect this pin to a 1% tolerance or better resistor divider between BP1V5 and AGND for different options of PMBus addresses and frequency sync (including determination of SYNC pin as SYNCIN or SYNCOUT function). See Programming ADRSEL.
VSEL	15	I	Connect this pin to a 1% tolerence or better resistor divider between BP1V5 and AGND for different options of internal voltage feedback dividers and default output voltage. See Programming VSEL.
MSEL2	16	I	Connect this pin to a 1% tolerence or better resistor divider between BP1V5 and AGND for different options of soft-start time, overcurrent fault limit, and multiphase information. See Programming MSEL2 or Programming MSEL2 for a Loop Follower Device (GOSNS Tied to BP1V5) for a loop follower device GOSNS tied to BP1V5.
EN/UVLO	19	I	Enable switching as the PMBus CONTROL pin. EN/UVLO can also be connected to a resistor divider to program input voltage UVLO.
PVIN	18,45	I	Input power to the power stage. Low-impedance bypassing of these pins to PGND is critical. PVIN to PGND must be bypassed with X5R or better ceramic capacitors rated for at least 1.5 × the maximum PVIN voltage.
AVIN	20	I	Input power to the controller
AGND	21	—	Analog ground return for controller. Connect the AGND pin directly to the thermal pad on the PCB board.
VDD5	22	O	Output of the 5V internal regulator. A bypassing capacitor is integrated and no external bypassing is required.
SYNC	28	I/O	For frequency synchronization, this pin can be programmed as SYNC IN or SYNC OUT pin by the ADRSEL pin or the (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG) PMBus command. SYNC pin can be left floating when not used.
VOUT	40, 41	O	Output of power module. Connect to output bypass capacitors to this pin.
Thermal Pad	42, 44	—	The thermal pad is the PGND pin made with a large area of copper to improve thermal conductivity to PCB. The thermal pad must have adequate solder coverage for best thermal performance.
SW	43	I/O	Switched power output of the device. Connect the output averaging filter and bootstrap to this group of pins if needed.
NC	24, 25, 26, 27, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38	—	No connection

(1) I = input, O = output