JAJSF47A April   2018  – May 2018 UCC28742

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
      2.      10W、5VのAC/DCコンバータの標準的な効率
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 VS (Voltage-Sense)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CS (Current Sense)
        6. 7.3.1.6 FB (Feedback)
      2. 7.3.2 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      3. 7.3.3 Control Law
      4. 7.3.4 Constant Current Limit and Delayed Shutdown
      5. 7.3.5 Valley-Switching and Valley-Skipping
      6. 7.3.6 Start-Up Operation
      7. 7.3.7 Fault Protection
    4. 7.4 Device Functional Modes
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  VDD Capacitance, CDD
        3. 8.2.2.3  VDD Start-Up Resistance, RSTR
        4. 8.2.2.4  Input Bulk Capacitance and Minimum Bulk Voltage
        5. 8.2.2.5  Transformer Turns Ratio, Inductance, Primary-Peak Current
        6. 8.2.2.6  Transformer Parameter Verification
        7. 8.2.2.7  VS Resistor Divider and Line Compensation
        8. 8.2.2.8  Standby Power Estimate
        9. 8.2.2.9  Output Capacitance
        10. 8.2.2.10 Feedback Loop Design Consideration
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
      2. 11.1.2 デバイスの項目表記
        1. 11.1.2.1  容量項(ファラッド単位)
        2. 11.1.2.2  デューティ・サイクル項
        3. 11.1.2.3  周波数項(ヘルツ単位)
        4. 11.1.2.4  電流項(アンペア単位)
        5. 11.1.2.5  電流および電圧のスケーリング項
        6. 11.1.2.6  変圧器の項
        7. 11.1.2.7  電力項(ワット単位)
        8. 11.1.2.8  抵抗項(オーム単位)
        9. 11.1.2.9  タイミング項(秒単位)
        10. 11.1.2.10 電圧項(ボルト単位)
        11. 11.1.2.11 AC電圧項(VRMS単位)
        12. 11.1.2.12 効率項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Transformer Turns Ratio, Inductance, Primary-Peak Current

The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at full load, the minimum input capacitor bulk voltage, and the estimated DCM resonant time.

Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have an estimate from previous designs. For the transition mode operation limit, the period required from the end of secondary current conduction to the first valley of the VDS voltage is ½ of the DCM resonant period, or 1 µs assuming 500-kHz resonant frequency. DMAX can be determined using Equation 10.

Equation 10. UCC28742 qu10_from_qu24_lusca8.gif

Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation below. DMAGCC is defined as the secondary diode conduction duty cycle when load current reaches a specified limit operation. It is set internally by the UCC28742 at 0.475. The total voltage on the secondary winding needs to be determined; which is the sum of VOCV and the secondary rectifier VF.

Equation 11. UCC28742 slusd71-equation5.gif

NPS is determined also with other design factors such as voltage and current ratings of primary MOSFET, secondary rectifier diode, as well as secondary MOSFET if synchronous rectifier is used. Once an optimum turns-ratio is determined from a detailed transformer design, use this ratio for the following parameters.

The UCC28742 controller constant current limit is achieved by maintaining DMAGCC = 0.475 at the maximum primary current setting. The transformer turns ratio and current limit determine the current sense resistor for a target constant current limit.

Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias power ratio to rated output power. A bias power can be initially estimated at 0.1% to 0.5% rated power depending on power rating. An overall transformer efficiency of 94.5% is a good estimation of assuming 2% leakage inductance, 3% core and winding loss, and 0.5% bias power.

RCS is used to program the primary-peak current with Equation 12:

Equation 12. UCC28742 qu12_from_qu26_lusca8.gif

The primary transformer inductance can be calculated using the standard energy storage equation for flyback transformers. Primary current, maximum switching frequency, output and transformer efficiency are included in Equation 14.

Initially the transformer primary current should be determined. Primary current is simply the maximum current sense threshold divided by the current sense resistance.

Equation 13. UCC28742 qu13_from_qu27_lusca8.gif
Equation 14. UCC28742 qu14_from_slusd71-equation2.gif

The primary inductance LP in Equation 14 also needs to consider primary MOSFET minimum turn on time as described in Transformer Parameter Verification.

The auxiliary winding to secondary winding transformer turns-ratio (NAS) is determined by the lowest target operating output voltage VOVL at current limit and above the VDD(off) of the UCC28742. The output voltage reaches VOVL when output current reaches its limit IOCC; VOVL is determined by IOCC and the expected minimum load resistance RLOAD at IOCC, i.e., VOVL = IOCC x RLOAD. Note that VOVL can only be maintained within typical 120ms, and after that time, the output voltage will enter the cycle of shutdown and auto-start retry, as described in Constant Current Limit and Delayed Shutdown, and shown in Figure 14 and Figure 15. There is additional energy supplied to VDD from the transformer leakage inductance energy which may allow a slightly lower turns-ratio to be used in a design. The NAS is then determined by the below equation.

Equation 15. UCC28742 qu15_from_qu29_lusca8.gif