10.1 Layout Guidelines

In general, try to keep all high current loop areas as small as possible. Keep all traces with high current and high frequency away from other traces in the design. If necessary, high frequency/high current traces should be perpendicular to signal traces, not parallel to them. Shielding signal traces with ground traces can help reduce noise pick up. Always consider appropriate clearances between the high-voltage connections and any low-voltage nets.

In order to increase the reliability and feasibility of the project it is recommended to adhere to the following guidelines for PCB layout. Figure 25 shows a typical 10-W, 5-V/2-A converter design schematics.

• Minimize stray capacitance on the VS node. Place the voltage sense resistors (R_S1 and R_S2 in) close to the VS pin.
• Arrange the components to minimize the loop areas of the switching currents as much as possible. These areas include such loops as the transformer primary winding current loop (a), the MOSFET gate-drive loop (b), the primary snubber loop (c), the auxiliary winding loop (d) and the secondary output current loop (e). In practice, trade-offs may have to be made. Loops with higher current should be minimized with higher priority. As a rule of thumb, the priority goes from high to low as (a) – (e) – (c) – (d) – (b).
• The R_LC resistor location is critical. To avoid any dv/dt induced noise (for example MOSFET drain dv/dt) coupled onto this resistor, it is better to place R_LC closer to the controller and avoid nearby the MOSFET.
• Using Kelvin connection for long distance connection such as for connection between optocoupler and FB pin.
• To improve thermal performance increase the copper area connected to GND pins.

Figure 25. 10-W, 5-V/2-A Converter Schematics