SBOA418 july   2023 OPA2197-Q1 , OPA392

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction: Open-Loop Output Impedance (RO)
  5. 2Overview: Closed-Loop Amplifier Stability
  6. 3Example, Calculate Optimal Isolation Resistance to Drive Large Load Capacitance
  7. 4RO, RISO, and Capacitive Load Drive
  8. 5Derive Equation for Optimal Isolation Resistance
  9. 6Summary
  10. 7References

RO, RISO, and Capacitive Load Drive

The output impedance, also referred to as output resistance, can be modeled as a series resistor at the output of the amplifier.

GUID-20230615-SS0I-TJ0Q-F4DF-H4VWD0T4CPT1-low.svgFigure 4-1 Op Amp Output Resistance Internal Model

The load capacitance (CLOAD) interacts with the output impedance of the amplifier (RO), producing an additional pole in the amplifier’s AOL curve, as shown in Figure 4-2. This additional pole (fp2) causes the AOL to decrease an additional 20 dB/decade resulting in a total of 40dB/decade rate of closure with 1/β. The rate of closure (ROC) is defined by the difference in slopes of the AOL and 1/β curves at the frequency in which the two curves intersect. A stable circuit exhibits a rate of closure of approximately 20 dB/decade.

Equation 3. fp2=12πROCLOAD
GUID-20230615-SS0I-2HSS-WWBG-T9M08FQ58GPM-low.svgFigure 4-2 Effects of Capacitive Load on Amplifier Open-Loop Gain

Considering the rate of closure between AOL and 1/β, stability issues arise when fp2 occurs at a frequency less than the bandwidth of the amplifier. For amplifiers with comparable bandwidth, an amplifier with lower open-loop output impedance is capable of driving larger capacitive loads, while maintaining stability.

When RISO is implemented in the circuit, the isolation resistance interacts with the load capacitance to produce a zero in the AOL curve. This zero (fz1) causes the AOL curve to increase by 20 dB/decade, canceling out the effect of fp2, and restoring the rate of closure to 20 dB per decade.

GUID-20230615-SS0I-KZF4-NNR9-SNP1ZQZZZJML-low.svg
Equation 4. fz1=12πRISOCLOAD
Figure 4-3 Op Amp Output Resistance with RISO and Capacitive Load

RISO also causes a shift in the pole frequency from fp2 to fp2* as defined in Equation 5.

Equation 5. fp2*=12π[RO+RISO]CLOAD
GUID-20230615-SS0I-R8FP-XQ54-G2PWL1C5PKBB-low.svgFigure 4-4 Effects of RISO on Amplifier Open-Loop Gain with Capacitive Load

RISO is designed to be as small as tolerable while maintaining closed-loop stability. A larger isolation resistor increases the phase margin, but at the cost of voltage error and settling time. If the load has a resistive element, RISO creates a resistor divider between the output of the amplifier and the load resistance, resulting in a voltage error. If the load resistance is much greater than RISO, this voltage error can be negligible. Figure 4-5 shows two amplifiers driving complex loads with a resistive element of 10 kΩ and 5 nF of capacitance. The voltage error caused by the 20 Ω isolation resistor can be tolerable for the application, whereas the 200 Ω isolation resistor produces an unacceptable error. For DC applications, if the RISO required to stabilize the amplifier is too large, the dual feedback method can be used. For AC applications, choose an op amp with a low output impedance to minimize the isolation resistance required for stability.

GUID-20230710-SS0I-DQZP-RKWS-GZT8Z7QMRD8L-low.svgFigure 4-5 RISO Voltage Divider with Resistive-Capacitive Load