SNVU821 November   2023 TPS92642-Q1

 

  1.   1
  2.   TPS92642EVM-203 5-A Synchronous Buck IR LED Driver Evaluation Module
  3.   Trademarks
  4. 1Introduction
  5. 2Warnings and Cautions
  6. 3Description
    1. 3.1 Typical Applications
    2. 3.2 Features
    3. 3.3 Connector and Test Point Description
    4. 3.4 Electrical Performance Specifications
  7. 4Test Setup
    1. 4.1 Input Supplies and LED Load Connections
    2. 4.2 Pulse Duty Cycle Limit (PLMT) Control
    3. 4.3 Analog Dimming Using IADJ
    4. 4.4 PWM Dimming Using nExt_PWM Test Points
    5. 4.5 Switching Frequency Set Point Using RON
  8. 5Performance Data and Typical Characteristic Curves
    1. 5.1 Efficiency
    2. 5.2 Analog Dimming
    3. 5.3 PWM Dimming
    4. 5.4 PWM Dimming Waveforms
  9. 6Schematic
  10. 7PCB Layout
  11. 8Bill of Materials

3.3 Connector and Test Point Description

This section describes the connectors and test points on the EVM and how to properly connect, setup, and use the TPS92642EVM-203.

GUID-20230911-SS0I-SQHR-9WBL-FTTW9JXWSQ0H-low.svgFigure 3-1 TPS92642EVM-203 Top View – EVM Functions and Features
GUID-20230911-SS0I-CCZ8-60Z1-7PL7WGRSC4P7-low.svgFigure 3-2 TPS92642EVM-203 Bottom View – EVM Functions and Features
Figure 3-3 and Table 3-1 describe the connector names, locations, and descriptions.
GUID-20230911-SS0I-FNZL-WSVD-7MDNNL2CGZFB-low.svg Figure 3-3 TPS92642EVM-203 Connector Names and Locations
Table 3-1 Connectors
Connector Description
J1 J1 allows for a creating a harness that connector to VOUT (pin 1) and GND (pin 2).
J2 J2 allows for a creating a harness that connector to VIN (pin 1) and GND (pin 2).

Figure 3-4 and Table 3-2 describe the test point names, locations, and descriptions.

GUID-20230911-SS0I-FVHK-SHPR-9HHZ5RBXLB23-low.svgFigure 3-4 TPS92642EVM-203 Test Point Names and Locations
Table 3-2 Test Points
Test PointDescription
GND (TP5, TP6, TP7)Larger metal turrets and test points allow for multiple connection to grounds across the board.
VIN (TP2)The VIN test point allows for voltage and current measurement of the power applied to the VIN pin of the
TPS92642-Q1.
VOUT (TP1)The VOUT+ test point allows for connection of the LED loads to the output. Large turrets allow for multiple connections.
SW (TP10)The SW test point allows for observing the switch node during operation with an oscilloscope.
PLMT (TP9)This test point is the test point used to monitor duty cycle limit control and pulse skipping control circuit. The PLMT pin is by default loaded with a 0.22-μF capacitor, which means it is providing a 13.62% duty cycle control of a 39-Hz PWM signal or an TON of 3.46 ms.
GUID-20220718-SS0I-KT2W-VRF4-BTQ68DG6VFBL-low.svg
nFLT (TP8)The nFLT test point can be used to monitor if a fault has occurrence on the TPS92642-Q1 output. When a fault occurs, nFLT voltage level goes low. nFLT is triggered when there is a SHORT or when there is an OPEN circuit fault.
GUID-20220718-SS0I-PXJP-QCBN-35KLCLXP1FJK-low.svg
IADJ (TP4)The TPS92642-Q1 LED current is controlled by applying a voltage to the IADJ test point. 133 mV to 2.45 V on IADJ test point (TP4) coincides with 288 mA to 5000 mA of output current.
GUID-20220628-SS0I-T6VQ-HR4W-SMDXCF7Q7T79-low.svg
UDIM (TP13)UDIM is the input for the external PWM signal. R4 sets the hysteresis and C8 is for local decoupling.
GUID-20220718-SS0I-C8RQ-ZZRN-RKW3TX3MNSGS-low.svg